Setting Operation Clock Of Watchdog Timer - Fujitsu F2MCTM-16LX Hardware Manual

Clearing overflow flag bit (WTC:WTOF)
When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait
time timer of subclock. The WTOF bit is cleared concurrently with mode switching.

Setting Operation Clock of Watchdog Timer

The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the
clock input source of the watchdog timer.
When using the subclock as the machine clock, always set the WDCS bit to 0 and select the output of the
watch timer.
Oscillation Stabilization Wait Time Timer of Subclock
When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation
stabilization wait time timer of subclock.
The subclock oscillation stabilization wait time is fixed at 2
Note:
Please consider the frequency difference of built-in CR oscillation when you use built-in CR oscillation
clock as a sub-clock.
CHAPTER 15 WATCH TIMER
14
/SCLK (SCLK: subclock frequency).
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