Selection Of A Pll Clock Multiplier - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 5 CLOCKS
Transition from sub-clock mode to main clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub-clock mode,
switching from the sub-clock to the main clock occurs after the main clock oscillation stabilization wait
interval.
Transition from PLL clock mode to sub-clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in PLL clock mode,
switching from the PLL clock to the sub-clock occurs.
Transition from sub-clock mode to PLL clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub-clock mode,
switching from the sub-clock to a PLL clock occurs after the main clock oscillation stabilization wait
interval.

Selection of a PLL Clock Multiplier

Writing the value from "000
register (CKSCR) and CS2 bit of the PLL/subclock control register (PSCCR) can select five types (1 to 4
multiplication and 6 multiplication) of PLL clock multiplier.
Machine Clock
PLL clock, main clock, and sub-clock outputted from the PLL multiplier circuit are used as machine clock.
This machine clock is supplied to the CPU and peripheral functions. The main clock, PLL clock, or sub-
clock can be selected by writing to the MCS or SCS bit of the clock selection register (CKSCR).
Notes:
Even though the MCS and SCS bits of the clock selection register (CKSCR) are rewritten, machine
clock switching does not occur immediately. When operating a resource that depends on the machine
clock, confirm that machine clock switching has been performed by referring to the MCM and SCM
bits of the clock selection register (CKSCR) before operating the resource.
When the MCS bit of the clock selection register (CKSCR) is "0" (PLL clock mode) and when the SCS
bit of the clock selection register (CKSCR) is "0" (sub-clock mode), the SCS bit is prioritized, and a
transition to the sub-clock mode is occurred.
When the clock mode is switched, do not switch to other clock mode and low-power consumption mode
before this switching is completed. Confirm the completion of clock mode switching by referring to the
MCM and SCM bits of the clock selection register (CKSCR).
If switching to other clock mode and low-power consumption mode is performed before a transition is
completed, the mode may not be switched.
104
" to "011 " and "110 " to the CS1 and CS0 bits of the clock selection
B B B