Fujitsu F2MCTM-16LX Hardware Manual page 205

At transition to the stop mode, the timebase timer counter is cleared to stop counting up. At return from the
stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock.
Figure 11.5-2 Example of Operation for Timebase Timer
Counter value
3FFFF
H
Oscillation
stabilization
waiting overflow
00000
H
Start CPU
operation
Power-on reset
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
STP bit
(LPMCR register)
When set the interval time select bit (TBTC:TBC1, TBC0) to "11
: Oscillation stabilization waiting time
HCLK : Oscillation clock
Clear by transferring to
stop mode
Interval cycle
(TBTC: TBC1: TBC0 = 11
Clear by interrupt process
Sleep
Cancellation of sleep at interval interrupt
of timebase timer
CHAPTER 11 TIMEBASE TIMER
Counter clear
)
(TBTC: TBR = 0)
B
Stop
19
"(2 /HCLK)
B
189