16-Bit Timer Registers (Tmr) - Fujitsu F2MCTM-16LX Hardware Manual

14.3.3

16-bit Timer Registers (TMR)

The 16-bit timer registers are 16-bit down counters. At read, the value being counted is
read.
16-bit Timer Registers (TMR)
Address:
TMR2 : 00794D
TMR3 : 00794F
Address:
TMR2 : 00794C
TMR3 : 00794E
R : Read only
X : Undefined
When the timer operation is enabled (TMCSR:CNTE = 1) and the start trigger is inputted, the value set in
the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count
operation.
When the timer operation is disabled (TMCSR:CNTE = 0), the TMR value is retained.
When the TMR value is counted down from "0000
underflow occurs.
[Reload mode]
When the TMR underflows, the value set in the TMRLR is reloaded to the TMR, restarting the TMR count
operation.
[One-shot mode]
When the TMR underflows, the TMR count operation is stopped, entering the start trigger input wait state.
The TMR value is retained to "FFFF
Notes:
• The TMR can be read during the TMR count operation. However, always use the word instruction
(MOVW).
• The TMR and the TMRLR are assigned to the same address. At write, the set value can be written to the
TMRLR without affecting the TMR. At read, the TMR value being counted can be read.
Figure 14.3-5 16-bit Timer Registers (TMR)
15 14 13 12
H
D15 D14 D13 D12
H
R R R R
7 6 5
H
D7 D6 D5
H
R R R
".
H
CHAPTER 14 16-BIT RELOAD TIMER
11 10 9 8
D11 D10 D9 D8
R R R R
4 3 2 1 0
D4 D3 D2 D1 D0
R R R R R
" to "FFFF " during the TMR count operation, an
H H
Reset value
XXXXXXXX
B
Reset value
XXXXXXXX
B
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