Fujitsu F2MCTM-16LX Hardware Manual page 675

Message Buffer Control Registers
Message Buffer Control Registers ..................... 452
Microcontroller
Connection of an Oscillator or an External Clock
to the Microcontroller.......................... 108
Minimum Connection
Example of Minimum Connection to Flash
Microcomputer Programmer ................ 563
Example of Minimum Connection to Flash
microcontroller Programmer ................ 561
Mode Data
Mode Data ...................................................... 164
Status of Pins after Mode Data is Read............... 132
Mode Fetch
Mode Fetch ..................................................... 127
Mode Pins
Mode Pins ............................................... 126, 163
Module Configuration
Module Configuration of 16-bit I/O Timer ......... 210
Multi-byte Data
Accessing Multi-byte Data.................................. 36
Multi-byte Data Allocation
Multi-byte Data Allocation in Memory Space ....... 36
Multi-level Message Buffer
Setting Configuration of Multi-level Message Buffer
.......................................................... 500
Multiple Interrupts
Multiple Interrupts ............................................. 71
Multiplier
Selection of a PLL Clock Multiplier .................. 104
N
NCC
Flag Change Disable Prefix (NCC) ...................... 49
Node Status
Correspondence between Node Status Bit and Node
Status................................................. 456
O
Operating Detection Reset Circuit
Block Diagram of Low Voltage/CPU Operating
Detection Reset Circuit........................ 374
Operating of Low Voltage/CPU Operating Detection
Reset Circuit....................................... 378
Sample Program for Low Voltage/CPU Operating
Detection Reset Circuit........................ 380
Operating Mode
CPU Intermittent Operating Mode ..................... 135
CPU Operating Modes and Current Consumption
.......................................................... 134
Operation Clock
Supply of Operation Clock................................ 191
Operation Enable Bit
Operation Enable Bit.........................................421
Operation Mode
CPU Intermittent Operation Mode......................142
Operation in Asynchronous LIN Mode
(operation mode 3)...............................429
Operation in Synchronous Mode (operation mode 2)
..........................................................426
Operation Modes of 16-bit Reload Timer............238
Setting for 16-bit PPG Output Operation Mode
..........................................................304
Setting for 8+8-bit PPG Output Operation Mode
..........................................................307
Setting for 8-bit PPG Output 2-channel
Independent Operation Mode................301
Operation Status
Operation Status during Standby Mode...............143
Oscillating Clock Frequency
Oscillating Clock Frequency and Serial Clock
Input Frequency...................................556
Oscillation Circuit
Prohibition Setting of CR Oscillation Circuit
and Clock Supervisor ...........................115
Reoperating Setting of CR Oscillation Circuit
and Clock Supervisor ...........................115
Oscillation Stabilization Wait
Oscillation Stabilization Wait and Reset State .....124
Oscillation Stabilization Wait Interval ................107
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time....................157
Oscillation Stabilization Wait Time Timer
of Subclock .........................................277
Reset Causes and Oscillation Stabilization Wait Times
..........................................................123
Oscillator
Connection of an Oscillator or an External Clock
to the Microcontroller ..........................108
Others
Others................................................................73
Overall Control Registers
List of overall Control Registers.........................446
Overall Control Registers ..................................452
P
Package Dimensions
Package Dimensions ...........................................12
PACSR
Address Detection Control Register 0 (PACSR0)
..........................................................509
Address Detection Control Register 1 (PACSR1)
..........................................................511
PADR
Detect Address Setting Registers (PADR0 to PADR5)
..........................................................513
INDEX
659