Timer Control Status Registers (Low) (Tmcsr: L) - Fujitsu F2MCTM-16LX Hardware Manual

14.3.2

Timer Control Status Registers (Low) (TMCSR: L)

The timer control status registers (Low) (TMCSR:L) enables or disable the timer
operation, check the generation of a software trigger or an underflow, enables or
disable an underflow interrupt, select the reload mode, and set the output of the TOT
pin.
Timer Control Status Registers (Low) (TMCSR: L)
Figure 14.3-4 Timer Control Status Registers (Low) (TMCSR: L)
Address:
TMCSR2 : 000064
H
TMCSR3 : 000066
H
R/W : Read/Write
: Reset value
∗
: For MOD0 (bit 7), see "14.3.1 Timer Control Status Registers (High) (TMCSR:H)".
7 6 5 4 3 2
∗
OUTE OUTL RELD INTE UF CNTE
R/W R/W R/W R/W R/W R/W R/W
bit5
TOT pin output level select bit
OUTL
One-shot mode (RELD=0)
High rectangular wave output
0
during counting
Low rectangular wave output
1
during counting
bit6
TOT pin output enable bit
OUTE
Pin function
0 General-purpose I/O port
1 TOT output
CHAPTER 14 16-BIT RELOAD TIMER
1 0
Reset value
TRG
0 0 0 0 0 0 0 0
B
bit0
TRG
0
1
bit1
CNTE
0
1
bit2
UF
0
1
bit3
INTE
0
1
bit4
RELD
0
1
Software trigger bit
No effect
After reloading, starts counting
Timer operation enable bit
Timer operation disabled
Timer operation enabled (wait start trigger)
Underflow generating flag bit
Read Write
No underflow Clear UF bit
Underflow No effect
Underflow interrupt enable bit
Underflow interrupt disable
Underflow interrupt enable
Reload select bit
One-shot mode
Reload mode
Reload mode (RELD=1)
Low toggle output at starting reload timer
High toggle output at starting reload timer
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