Watchdog Timer Control Register (Wdtc) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 12 WATCHDOG TIMER
12.3.1

Watchdog timer control register (WDTC)

The watchdog timer control register starts and clears the watchdog timer, sets the
interval time, and holds reset factors.
Watchdog Timer Control Register (WDTC)
7 6
Address
PONR WRST ERST SRST WTE WT1
0000A8
H
R
R : Read only
W : Write only
X : Undefined
*1 : The previous state is held.
*2 : However, SCLK is 2 division or 4 division of the clock inputted to the low-speed oscillation pin (X0A and
X1A) or internal CR oscillation clock. The division ratio is set by the SCDS bit of the PLL/subclock control
register (PSCCR). (See "CHAPTER 5 CLOCKS".)
See Table 12.1-1 for the interval time.
202
Figure 12.3-2 Watchdog Timer Control Register (WDTC)
0
5 4 3 2 1
WT0
R R R W W W
WT1 WT0
HCLK: Oscillation clock
The parenthesized values are interval time when the oscillation clock
operates at HCLK 4 MHz.
SCLK: Sub clock*
The parenthesized values are interval time when the oscillation clock
WTE
PONR WRST ERST SRST
Reset value
XXXXX111
B
bit1 bit0
Interval time select bit (timebase timer output select)
Interval time
Min
0 0 approx. 3.58 ms approx. 4.61 ms
0 1 approx. 14.33 ms approx. 18.3 ms
approx. 57.23 ms approx. 73.73 ms
1 0
1 1 approx. 458.75 ms approx. 589.82 ms
bit1 bit0
WT1 WT0 Interval time select bit (watch timer output select)
Interval time
Min
0 0 approx. 0.457 s approx. 0.576 s
0 1 approx. 3.584 s approx. 4.608 s
1 0 approx. 7.168 s approx. 9.216 s
1 1 approx. 14.336 s approx. 18.432 s
2
bit2
Watchdog timer control bit
0 First programming after reset:
Start up the watchdog timer
1 No effect
bit7 bit5 bit4 bit3
Reset factor bit
1 X X X Power-on reset
1 1 1 1 Watchdog reset
* * *
1 1 1 1 External reset (Low level input to RST pin)
* * *
1 1 1 1 Software reset (write "1" to RST bit)
* * *
Clock cycle
Max
14 ± 2 11
2 /HCLK
16 ± 2 13
2 /HCLK
18 ± 2 15
2 /HCLK
21 18
± 2
2 /HCLK
Clock cycle
Max
12 9
± 2
2 /SCLK
15 12
± 2
2 /SCLK
16 ± 2 13
2 /SCLK
17 ± 2 14
2 /SCLK
Twice or more programming after reset :
Clear the watchdog timer
Reset factor