Fujitsu F2MCTM-16LX Hardware Manual page 63

2.8-1 . DPR is eight bits long, and is initialized to 01
instruction.
Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode
DTB register
MSB
24-bit physical address
Program counter bank register (PCB) <Initial value: Value in reset vector>
Data bank register (DTB) <Initial value: 00
User stack bank register (USB) <Initial value: 00
System stack bank register (SSB) <Initial value: 00
Additional data bank register (ADB) <Initial value: 00
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated. All bank registers are one byte long. PCB is initialized to 00
than PCB can be read or written to. PCB can be read but cannot be written to.
PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16M
bytes space is executed or when an interrupt occurs. For operation of each register, see "2.2 Memory
Space".
by a reset. DPR can be read or written to by an
H
DPR register
>
H
>
H
>
H
>
H
CHAPTER 2 CPU
Direct address during instruction
LSB
by a reset. Bank registers other
H
47