Program Example Of 16-Bit I/O Timer - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 13 16-Bit I/O TIMER
13.8

Program Example of 16-bit I/O Timer

This section gives a program example of the 16-bit I/O timer.
Program Example of 16-bit I/O Timer
Processing specification
• The cycle of a signal input to the IN0 pin is measured.
• The 16-bit free-run timer 0 and input capture 0 are used.
• The rising edge is selected as the trigger to be detected.
• The machine clock ( φ ) is 24 MHz and the count clock of the free-run timer is 4/ φ (0.17 µs).
• The timer overflow interrupt and input capture interrupt of input capture 0 are used.
• The overflow interrupt of the 16-bit free-run timer is counted beforehand and used for the cycle
calculation.
• The cycle can be determined from the following equation:
Cycle = (overflow count × "10000
= (overflow count × 10000
Coding example
ICR09
ICR11
DDR2
TCCSL
TCDT
ICS01
IPCP0
IVF0
ICP0
DATA
OV_CNT RW
DATA
;
;---------Main program-------------------------------------------
CODE
START:
;
234
" + nth IPCP0 value - (n-1)th IPCP0 value) × count clock cycle
H
+ nth IPCP0 value - (n-1)th IPCP0 value) × 0.17 µs
H
EQU 0000B9H
EQU 0000BBH
EQU 000012H
EQU 007942H
EQU 007940H
EQU 000050H
EQU 007920H
EQU TCCSL:7
EQU ICS01:6
DSEG ABS=00H
ORG 0100H
1H
ENDS
CSEG
AND CCR,#0BFH
MOV I:ICR09,#00H
MOV I:ICR11,#00H
MOV I:DDR2,#00000000B
MOV I:TCCSL,#01001010B ;Count enable, Counter clear,
;Interrupt control register
;Interrupt control register
;Port 2 direction register
;Timer control status register
;Timer data register
;Input capture control status register
;Input capture register 0
;Timer overflow generation flag bit
;Valid edge detection flag bit
;Overflow count counter
;Stack pointer (SP),
;already initialized
;Interrupt disable
;Interrupt level 0(strongest)
;Interrupt level 0(strongest)
;Port 2 direction setting
;Overflow, Interrupt enable,
;Count clock selection, Counter clear