Fujitsu F2MCTM-16LX Hardware Manual page 527

Address Detection Control Register 1 (PACSR1)
Figure 22.3-3 Address Detection Control Register 1 (PACSR1)
15 14
Address
Re- Re-
0 0 0 0 3 B
served served
H
R/W R/W
R/W Read/Write
: Reset value
13 12 11 10 9 8
Re- Re- Re-
AD5E AD4E AD3E
served served served
R/W R/W R/W R/W R/W R/W
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Reset value
0 0 0 0 0 0 0 0
B
bit 8
Reserved
0 Always set to "0".
bit 9
AD3E Address match detection enable bit 3
0 Disables address match detection in PADR3.
1 Enables address match detection in PADR3.
bit 10
Reserved
0 Always set to "0".
bit 11
AD4E Address match detection enable bit 4
0 Disables address match detection in PADR4.
1 Enables address match detection in PADR4.
bit 12
Reserved
0 Always set to "0".
bit 13
AD5E Address match detection enable bit 5
0 Disables address match detection in PADR5.
1 Enables address match detection in PADR5.
bit 14
Reserved
0 Always set to "0".
bit 15
Reserved
0 Always set to "0".
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
511