Ppgc/D Count Clock Select Register (Ppgcd) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 16 8-/16-BIT PPG TIMER
16.3.3

PPGC/D Count Clock Select Register (PPGCD)

The PPGC/D count clock select register selects the count clock of the 8-/16-bit PPG
timers C and D and the output pin.
This section explains the PPGCD function only. The PPGEF has the same function as
the PPGCD, and the 8-/16-bit PPG timers E and F are set.
PPGC/D Count Clock Select Register (PPGCD)
Address:
chD PPGCD 00004A
Other channel:
chF PPGEF 00004E
: Read/Write
R/W
X
: Indeterminate
−
: Undefined
: Reset value
HCLK : Oscillation clock
φ
: Machine clock frequency
The parenthesized values are provided when the oscillation clock operates at
4 MHz and the machine clock operates at 24 MHz.
n = C, E
m = n+1
296
Figure 16.3-4 PPGC/D Count Clock Select Register (PPGCD)
7 6
5 4 3
H
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
R/W R/W R/W R/W R/W
H
2 1 0
Reset value
REV
0 0 0 0 0 0 X 0
−
R/W R/W
bit 0
REV
0
Output pulse from standard output pin
1
Switch output pin between PPGn and PPGm
bit 4 bit 3 bit 2
PCM2 PCM1 PCM0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
bit 7 bit 6 bit 5
PCS2 PCS1 PCS0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
B
PPG output pin select bit
PPGC
count clock select bits
φ
0
1/ (41.7 ns)
φ
1
2/ (83.3 ns)
φ
2
0
2 / (167 ns)
φ
3
1
2 / (333 ns)
φ
4
0
2 / (667 ns)
1
Setting disable
0
Setting disable
µ
9
1
2 /HCLK(128 s)
PPGD
count clock select bits
φ
0
1/ (41.7 ns)
φ
1
2/ (83.3 ns)
φ
2
0
2 / (167 ns)
φ
3
1
2 / (333 ns)
φ
4
0
2 / (667 ns)
1
Setting disable
0
Setting disable
µ
9
1
2 /HCLK(128 s)