Fujitsu F2MCTM-16LX Hardware Manual page 447

Figure 20.7-8 LIN-UART Behavior as Slave in LIN Mode
Serial
clock
Serial input
(LIN bus)
LBD
ICU input
signal
(LSYN)
LIN bus timing
Figure 20.7-9 LIN Bus Timing and LIN-UART Signals
Old serial clock
LIN
bus
(SIN)
RXE
LBD
(IRQ0)
LBIE
ICU input
(LSYN)
IRQ(ICU)
RDRF
(IRQ0)
RIE
Read
RDR
Reception inter-
by CPU
rupt enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD->0)
IRQ cleared: Begin of ICU
IRQ cleared: Calculate & set new baud rate
Synch break (at 14-bit setting)
No clock used
(calibration frame)
ICU count
IRQ (ICU)
IRQ(ICU)
LBIE disable
Reception enable
Falling edge of start bit
Store one byte of received data to RDR
LBR cleared by CPU
Synch field
New (calibrated) serial clock
RDR read by CPU
CHAPTER 20 LIN-UART
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