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CHAPTER 8 LOW-POWER CONSUMPTION MODE
Table 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR)
bit7
bit6
bit5
bit4
bit3
bit1
bit2
bit0
140
Bit name
STP:
This bit transits to the stop mode.
Stop mode bit
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the stop mode.
Read: "0" is always read.
•
SLP:
This bit shift to sleep mode
Sleep mode bit
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the sleep mode.
Read: "0" is always read.
•
•
SPL:
The bit is used to set the state of input/output pins after transition to the stop
Pin state specification bit
mode, watch mode, or timebase timer mode.
When the bit is set to "0": The current level of input/output pins is held.
When the bit is set to "1": The I/O pins enter a high impedance state.
•
RST:
This bit generates software reset.
Internal reset signal
When the bit is set to "0": An internal reset signal for three machine cycles
generation bit
When the bit is set to "1": No effect
Read: "1" is always read.
TMD:
This bit shift to watch mode or timebase timer mode
Watch mode bit
When the bit is set to "0": If the main clock mode or PLL clock mode is
When the bit is set to "1": No effect
•
Read: "1" is always read.
CG1, CG0:
These bits are used to set the halt cycle count of the CPU clock in the CPU
CPU suspended cycle
intermittent operation mode.
number select bits
•
Reserved: reserved bit
Always set this bit to "0".
The bit is initialized to "0" when a reset or external interrupt occurs.
The bit is initialized to "0" when a reset or external interrupt occurs.
When the STP and SLP bits are set to "1" at the same time, the STP bit
supersedes the SLP bit, causing a transition to stop mode.
The bit is initialized to "0" at a reset.
is generated.
used, the bit transits to the timebase timer mode.
If the sub-clock mode is used, the bit transits to
the watch mode.
The bit is set to "1" when a reset or interrupt occurs.
Any reset causes the bit to return to the reset value.
Function
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