Extended Status/Control Register (Escr) - Fujitsu F2MCTM-16LX Hardware Manual

20.4.5

Extended Status/Control Register (ESCR)

This register provides several LIN functions, direct access to the SINn and SOTn pins
and setting of continuous clock output and sampling clock edge in LIN-UART
synchronous clock mode.
Extended Status/control Register (ESCR)
Figure 20.4-6 shows the Configuration of the extended status/control register (ESCR), and Table 20.4-4
shows the function of each bit.
Figure 20.4-6 Configuration of the Extended Status/control Register (ESCR)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
ESCR0 : 000025
H
LBIE
ESCR1 : 00002D
H
R/W
R/W : Read/Write
×
: Undefined
: Initial value
bit 9
LBD LBL1 LBL0 SOPE SIOP CCO SCES
R/W R/W R/W R/W R/W R/W
Initial value
bit 8 bit 7 bit 0
00000100
R/W
bit 8
SCES Sampling Clock Edge Selection Bit (Mode 2)
0 Sampling on rising clock edge (normal)
1 Sampling on falling clock edge (inverted clock)
bit 9
CCO Continuous Clock Output Enable Bit (Mode 2)
0 Continuous Clock Output disabled
1 Continuous Clock Output enabled
bit 10
Serial Input/Output Pin Access
SIOP
write (SOPE = "1")
0 SOTn pin is forced to "0"
1 SOTn pin is forced to "1"
bit 11
SOPE Serial Output pin direct Access Enable Bit
0 Serial Output pin direct access disable
1 Serial Output pin direct access enable
bit 12 bit 13
LBL0 LBL1 LIN Synch break length select bit
0 0 LIN break length 13-bit times
1 0 LIN break length 14-bit times
0 1 LIN break length 15-bit times
1 1 LIN break length 16-bit times
bit 14
LIN Synch break detected flag bit
LBD
write
Clear LIN synch break detected
0
flag
1 Ignored
bit 15
LBIE LIN Synch break detection Interrupt enable bit
0 LIN Synch break detection interrupt disable
1 LIN Synch break detection interrupt enable
CHAPTER 20 LIN-UART
B
read
Reading the actual value of
SINn pin
read
No LIN synch break
detected
LIN synch break detected
401