Input Capture Control Status Registers (Ics) - Fujitsu F2MCTM-16LX Hardware Manual

13.3.4

Input Capture Control Status Registers (ICS)

The function of the input capture control status register is shown below.
The correspondence between ICS01 to ICS23 and input pin is as follows.
• ICS01: IN0, IN1 input capture ch0, ch1
• ICS23: IN2, IN3 input capture ch2, ch3
Input Capture Control Status Registers (ICS01, ICS23)
Address
ICS01 : 000050
H
ICS23 : 000052
ICPm ICPn ICEm ICEn EGm
H
R/W
R/W : Read/Write
: Reset value
Figure 13.3-4 Input Capture Control Status Registers (ICS)
7 6 5 4 3 2
1 EGm0 EGn1
R/W R/W R/W R/W R/W
1 0
Reset value
EGn0
0 0 0 0 0 0 0 0
R/W R/W
bit1 bit0
EGn1 EGn0
0 0
Without edge detection (operation stop state)
0 1 Detect rising edge
1 0 Detect falling edge
1 1 Detect both edges
bit3 bit2
EGm1 EGm0
0 0 Without edge detection(operation stop state)
0 1 Detect rising edge
1 0 Detect falling edge
1 1 Detect both edges
bit4
ICEn
0 Input capture 0 interrupt disable
1 Input capture 0 interrupt enable
bit5
ICEm
0 Input capture 1 interrupt disable
1 Input capture 1 interrupt enable
bit6
ICPn
Read
Input capture 0 without
0
valid edge detection
Input capture 0 with valid
1
edge detection
bit7
ICPm
Read
Input capture 1 without
0
valid edge detection
Input capture 1 with valid
1
edge detection
n = 0, 2
CHAPTER 13 16-Bit I/O TIMER
B
Edge select bit n
Edge select bit m
Capture interrupt enable bit n
Capture interrupt enable bit m
Valid edge detection flag bit n
Write
Clear of ICP0 bit
No effect
Valid edge detection flag bit m
Write
Clear of ICP1 bit
No effect
m = n + 1
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