Serial Control Register (Scr) - Fujitsu F2MCTM-16LX Hardware Manual

20.4.1

Serial Control Register (SCR)

This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
transmission and reception.
Serial Control Register (SCR)
Figure 20.4-2 Configuration of the Serial Control Register (SCR)
Address
bit15
SCR0 : 000021
H
PEN
SCR1 : 000029
H
R/W
R/W : Read/Write
W : Write only
: Initial value
bit14 bit13 bit12 bit11
bit10
CL
SBL AD CRE RXE TXE
P
R/W R/W
R/W R/W
W
bit9 bit7
bit8
R/W R/W
bit8
TXE Transmission operation enable bit
0 Disable transmission
1 Enable transmission
bit9
RXE Reception operation enable bit
0 Disable reception
1 Enable reception
bit10
Clear reception error flag bit
CRE
0 No effect
Clear all reception error flags
1
(PE, FRE, ORE)
bit11
AD Address/data format select bit
0 Data frame
1 Address frame
bit12
CL
0 7 bits
1 8 bits
bit13
SBL
0 1 bit
1 2 bits
bit14
P
0 Even parity enabled
1 Odd parity enabled
bit15
PEN
0 Parity disabled
1 Parity enabled
CHAPTER 20 LIN-UART
bit0 Initial value
00000000
B
Write Read
Read
always
returns 0
Data length select bit
Stop bit length select bit
Parity select bit
Parity enabled bit
393