Block Diagram Of Can Controller - Fujitsu F2MCTM-16LX Hardware Manual

21.2

Block Diagram of CAN Controller

Figure 21.2-1 shows a block diagram of the CAN controller.
Block Diagram of CAN Controller
2
F MC-16LX bus
Clock
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
NS1, 0
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
IDR0 to 15,
DLCR0 to 15,
DTR0 to 15,
RAM
LEIR
IDER
Figure 21.2-1 Block Diagram of CAN Controller
Prescaler
Bit timing generation
1 to 64 frequency division
Node status change Node status
interrupt generation change interrupt
TBFx clear
Transmitting buffer
TBFx
x decision
TBFx
TBFx, set, clear
Transmission complete Transmission
interrupt generation complete
interrupt
RBFx, set
Reception
Reception complete
complete
interrupt generation
interrupt
RBFx, TBFx, set, clear
IDSEL
RBFx, set
0
Receiving buffer
1
Acceptance
to decision
filter
RBFx
RAM address
RBFx, TBFx, RDLC, TDLC, IDSEL
generation
TQ (Operating clock)
SYNC, TSEG1, TSEG2
Bus state
machine
Error
control
Transmitting/
receiving sequencer
Data Acceptance
counter filter control
TDLC RDLC IDSEL
BITER, STFER,
ARBLOST
CRCER, FRMER,
ACKER
Transmission
shift register
CRC
generation
TDLC
CRCER
RDLC
CRC generation/error
check
Receive shift Destuffing/stuffing
register
ARBLOST
BITER
Acknowledgment
ACKER
FRMER
IDLE, SUSPND,
transmit, receive,
ERR, OVRLD
Error frame
generation
Overload
frame
generation
Output
TX
driver
Stuffing
ACK
generation
STFER
error check
Arbitration
check
Bit error
check
PH1
error check
Input
Form error
RX
latch
check
445