Fujitsu F2MCTM-16LX Hardware Manual page 146

CHAPTER 7 RESETS
Status of Reset Cause Bit and Low Voltage Detection Bit
Figure 7.5-3 Status of Reset Cause Bit and Low Voltage Detection Bit
PONR bit
(power-on)
ERST bit (external reset
input, CPU operation detection,
or LVRF = 1)
LVRF bit*
(low voltage detection
4V
*: The LVRF bit exist in the low voltage/CPU operation detection reset control register (LVRC).
(1) At power-on
Power-on reset bit (PONR) , ERST, and LVRF are set to "1" at power on.
(2) Bit clear
Bit is cleared by reading the WDTC register and by writing "0" to LVRF.
(3) At low voltage detection (4.0 V ± 0.3 V)
The LVRF and ERST bits are set to "1" at low voltage detection of V
(4) Bit clear
Bit is cleared by reading the WDTC register and by writing "0" to LVRF.
130
Flag status
at power-on
Vcc=4V
Vcc
0.3V)
Flag status at
Bit low voltage
clear detection (4V)
(1) (2) (3)
1 0 0
1 0 1
or
0
1 0 1
or
0
Bit
clear
(4)
0
0
0
= 4.0 V ± 0.3 V.
CC