Port Direction Register (Ddr) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 10 I/O PORTS
10.2.2

Port Direction Register (DDR)

This register has following functions:
• Setting the data direction of each pin that is used as a port.
• Setting the input level of SIN -- Serial data input pin for LIN-UART.
Port Direction Register (DDR)
Figure 10.2-3 shows the Port Direction Registers (DDR).
DDR2
Address: 000012
DDR4
Address: 000014
DDR5
Address: 000015
DDR6
Address: 000016
DDR8
Address: 000018
DDRA
Address: 00001A
Bits Dxx (DDR2, DDR4 to DDR6, DDR8)
These bits set to the I/O direction of the port. When each pin is used as port, the corresponding pin is
controlled below.
When set to "0": The corresponding pin is set to input mode.
When set to "1": The corresponding pin is set to output mode.
Bits SIL0, SIL1 (DDRA bit3, bit4)
These bits set the input level of the corresponding SIN (Serial Data Input for LIN-UART) pin forcibly.
SIL0 to SIL1 correspond to SIN0 (LIN-UART0) to SIN1(LIN-UART1), respectively.
When setting to "0": CMOS or Automotive is selected for the input level depending on the setting of the
When set to "1":
The initial value of these bits is "0".
172
Figure 10.2-3 Port Direction Registers (DDR)
Bit No.
7 6
D27 D26
H
Bit No.
7 6
H
Bit No.
7 6
D57 D56
H
Bit No.
7 6
D67 D66
H
Bit No.
7 6
D87 D86
H
Bit No.
7 6
H
corresponding ILx bit and ILTx bit in the ILSR. (See "10.2.5 Input Level Select
Register" for ILSR.)
CMOS is selected for the input level regardless of the setting of the corresponding
ILx bit and ILTx bit in ILSR.
5 4 3 2 1
D25 D24 D23 D22 D21
5 4 3 2 1
D44 D43 D42 D41
5 4 3 2 1
D55 D54 D53 D52 D51
5 4 3 2 1
D65 D64 D63 D62 D61
5 4 3 2 1
D85 D84 D83 D82
5 4 3 2 1
SIL1 SIL0
W W
Reset value Access
0
D20 00000000 R/W
B
0
D40 XXX00000 R/W
B
0
D50 00000000 R/W
B
0
D60 00000000 R/W
B
0
D80 000000X0 R/W
B
0
Access
XXX00XXX
B