Receive Overrun Register (Rovrr) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.19

Receive Overrun Register (ROVRR)

If RCx of the reception complete register (RCR) is 1 when completing storing of a
received message in the message buffer (x), ROVRx becomes 1, indicating that
reception has overrun.
Register Configuration
Figure 21.4-19 Configuration of the Receive overrun Register (ROVRR)
Address
CAN1: 00008D
Address
CAN1: 00008C
R/W : Read/Write
Register Function
Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception
has overrun, write 0 to ROVRx to set it to 0.
1 is read when a Read-Modify-Write instruction is performed.
Note:
If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.
bit15 bit14 bit13
RVOR15 RVOR14 RVOR13
H
R/W R/W R/W
bit7 bit6 bit5
RVOR7 RVOR6 RVOR5
H
R/W R/W R/W
bit12 bit11 bit10
RVOR12 RVOR11 RVOR10 RVOR9
R/W R/W R/W
bit4 bit3 bit2
RVOR4 RVOR3 RVOR2 RVOR1
R/W R/W R/W
bit9 bit8 ROVRR1(Upper)
RVOR8 Reset value
0 0 0 0 0 0 0 0
R/W R/W
bit1 bit0 ROVRR1(Lower)
RVOR0 Reset value
0 0 0 0 0 0 0 0
R/W R/W
B
B
475