Block Diagram Of The Clock Generation Block - Fujitsu F2MCTM-16LX Hardware Manual

5.2

Block Diagram of the Clock Generation Block

The clock generation block consists of five blocks:
• System clock generation circuit/sub-clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• PLL/sub-clock control register (PSCCR)
• Oscillation stabilization wait interval selector
Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block. The figure also includes the standby
control circuit and timebase timer circuit.
RST Pin
Reset (Clear)
Interrupt (Clear)
Clock
generator
CS2
PLL/Subclock
Control register
(PSCCR):bit8
Pin
X0
X1
Pin
oscillation clock
oscillation circuit
Pin
X0A
X1A
Pin
Internal CR oscillation clock
Subclock oscillation circuit
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low-Power consumption Mode Control Register(LPMCR)
STP SLP
Operation clock
selector
PLL multiplier
circuit
Clock
selector
Clock
selector
Clock supervisor function
SPL RST TMD CG1 CG0
Reserved
CPU intermittent
operation cycle
selector
Standby
2
Control circuit
SCM MCM WS1 WS0 SCS
Clock selection register (CKSCR)
2- 512-
divided divided
divided
Main
oscillation
clock
clock (HCLK)
Timebase timer
Subclock
(SCLK)
1024
4-divided/
-divided
2-divided
Clock timer
SCDS
PLL/Subclock
control register
(PSCCR):bit10
CHAPTER 5 CLOCKS
Terminal high
impedance Pin High-z control
Control circuit
Internal reset
Internal reset
generator
Select the intermitted cycle
CPU clock
CPU operating clock
Control circuit
Time, sleep, stop sign
Time, stop sign
Peripheral function
Peripheral Clock
Control circuit operating clock
Subclock oscillation stabilization wait clear
Main clock oscillation stabilization wait clear
Machine
Clock
Oscillation
stabilization
2
wait time selector
2
MCS CS1 CS0
4- 2- 2- 2- 2-
divided divided divided divided
To watchdog timer
8- 2-
divided divided
2- 4-
divided divided
2-
divided
95