Fujitsu F2MCTM-16LX Hardware Manual page 26

CHAPTER 1 OVERVIEW
Figure 1.2-2 Block Diagram of Evaluation Chip (MB90V340A-103/104)
X0,X1
X0A,X1A *
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
AV cc
AV ss
AN23 to AN0
AVRH
AVRL
ADTG
DA01 , DA00
PPGF to PPG0
SDA1 , SDA0
SCL1 , SCL0
: Support MB90V340A-104 only
*
10
Clock
control
2
F MC-16LX core
CR
oscillation
circuit
RAM 30KB
Prescaler
(5 channels)
UART
5 channels
8-/10-bit
A/D
converter
24 channels
10-bit D/A
converter
2 channels
8-/16-bit
PPG
16 channels
2
I C
Interface
2 channels
DMA
16-bit
I/O timer 0
Input
capture
IN7 to IN0
8 channels
Output
compare
OUT7 to OUT0
8 channels
16-bit
I/O timer 1
CAN
RX2 to RX0
controller
TX2 to TX0
3 channels
16-bit
TIN3 to TIN0
reload timer
TOT3 to TOT0
4 channels
AD15 to AD00
A23 to A16
External
bus
DTP/
INT15 to INT8
external
(INT15R to INT8R)
interrupt
INT7 to INT0
Clock
monitor
FRCK0
FRCK1
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
CKOT