Block Diagram Of Input Capture - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 13 16-Bit I/O TIMER
13.2.2

Block Diagram of Input Capture

The input capture consist of the following blocks:
Block Diagram of Input Capture
IN3
Pin
IN2
Pin
IN1
Pin
LIN-UART1
IN0
Pin
LIN-UART0
214
Figure 13.2-3 Block Diagram of Input Capture Unit 0
Edge detection circuit
Input capture control
status register (ICS23)
Input capture control
status register (ICS01)
2
Edge detection circuit
16-bit free-run timer
Input capture data register 3 (IPCP3)
Input capture data register 2 (IPCP2)
Input capture edge
register (ICE23)
2
2
ICP3 ICP2 ICE3 ICE2 EG31 EG30
ICP1 ICP0 ICE1 ICE0 EG11 EG10
2
Input capture edge register (ICE01)
ICUS1
ICUS0
Input capture data register 1 (IPCP1)
Input capture data register 0 (IPCP0)
IEI3 IEI2
EG21 EG20
Input capture
interrupt request
EG01 EG00
IEI1 IEI0