Fujitsu F2MCTM-16LX Hardware Manual page 603

Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+
Before execution
After execution
Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
A, @RW1+10H
MOVW
Before execution
After execution
Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H
Before execution
After execution
(This instruction reads data by register indirect addressing with post
increment and stores it in A.)
A 0 7 1 6
RW1 D 3 0 F
A 2 5 3 4
RW1 D 3 1 1
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
(This instruction reads data by register indirect addressing with an
offset and stores it in A.)
A 0 7 1 6
RW1 D 3 0 F
A 2 5 3 4
RW1 D 3 0 F
(This instruction reads data by long register indirect addressing with an
offset and stores it in A.)
A 0 7 1 6
RL2 F 3 8 2 4 B 0 2
A 2 5 3 4
RL2 F 3 8 2 4 B 0 2
2 5 3 4
Memory space
DTB 7 8 78D310H
78D30FH
F F E E
DTB 7 8
2 5 3 4
Memory space
DTB 7 8 78D320H
78D31FH
(+10H)
F F E E
DTB 7 8
2 5 3 4
Memory space
824B28H
824B27H
(+25H)
F F E E
APPENDIX B Instructions
F F
E E
F F
E E
F F
E E
587