Reset Causes And Oscillation Stabilization Wait Times; Reset Cause And Oscillation Stabilization Wait Times - Fujitsu F2MCTM-16LX Hardware Manual

7.2

Reset Cause and Oscillation Stabilization Wait Times

The MB90360 series has seven reset causes. The oscillation stabilization wait time for a
reset depends on the reset cause.

Reset Causes and oscillation Stabilization Wait Times

Table 7.2-1 summarizes reset causes and oscillation stabilization wait times.
Table 7.2-1 Reset Causes and oscillation Stabilization Wait Times
Reset
Power-on Power-on
Watchdog Watchdog timer overflow
External L input from RST pin
Software Write "0" to RST bit of low-power
consumption mode control register
(LPMCR)
Low voltage When low voltage is detected
1
detection *
CPU operation When CPU operation detection counter
overflows
1
detection *
2
When failure of main clock/subclock is
Clock supervisor *
detected
HCLK: Oscillation clock frequency
WS1, WS0: Oscillation stabilization wait time select bit of clock selection register (CKSCR)
*1: Product with T-suffix
*2: For MB90F367/T(S), MB90367/T(S)
Figure 7.2-1 shows the oscillation stabilization wait times at a power-on reset.
Reset cause Oscillation stabilization wait time
The parenthesized values are provided when
oscillation clock frequency operates at 4 MHz
16
2 /HCLK (approx. 16.38 ms)
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
None
Note: However, the WS1 and WS0 bits are initialized to
"11".
CHAPTER 7 RESETS
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