Fujitsu F2MCTM-16LX Hardware Manual page 585

Table A-1 I/O Map (2/5)
Address
000019
Reserved
H
00001A
Port A direction register
H
00001B to
H
Reserved
00001D
H
00001E
Port 2 pull-up control register
H
00001F
Reserved
H
000020
Serial mode register 0
H
000021
Serial control register 0
H
000022
Reception/transmission data register 0
H
000023
Serial status register 0
H
Extended communication control
000024
H
register 0
000025
Extended status control register0
H
000026
Baud rate generator register 00
H
000027
Baud rate generator register 01
H
000028
Serial mode register 1
H
000029
Serial control register 1
H
00002A
Reception/transmission data register 1
H
00002B
Serial status register 1
H
Extended communication control
00002C
H
register1
00002D
Extended status control register 1
H
00002E
Baud rate generator register 10
H
00002F
Baud rate generator register 11
H
000030 to
H
Reserved
00003A
H
00003B
Address detection control register 1
H
00003C to
H
Reserved
000047
H
000048
PPGC operation mode control register
H
000049
PPGD operation mode control register
H
00004A
PPGC /D count clock selection register
H
Register Abbreviation
DDRA
PUCR2
SMR0
SCR0
RDR0/TDR0 R/W
SSR0
ECCR0
ESCR0
BGR00
BGR01
SMR1
SCR1
RDR1/TDR1 R/W
SSR1
ECCR1
ESCR1
BGR10
BGR11
PACSR1
PPGCC
PPGCD
PPGCD
Access Peripheral
W Port A
R/W Port 2
W, R/W
W, R/W
R, R/W
UART0
R, W, R/W
R/W
R/W, R
R/W, R
W, R/W
W, R/W
R, R/W
UART1
R, W, R/W
R/W
R/W, R
R/W, R
Address Match
R/W
Detection 1
W, R/W
16-bit
W, R/W
PPGC/D
R/W
APPENDIX A I/O Maps
Initial value
XXX0 0XXX
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 1 0 0 0
B
0 0 0 0 0 0 XX
B
0 0 0 0 0 1 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 1 0 0 0
B
0 0 0 0 0 0 XX
B
0 0 0 0 0 1 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 X 0 0 0 XX1
B
0 X 0 0 0 0 0 1
B
0 0 0 0 0 0 X 0
B
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