Fujitsu F2MCTM-16LX Hardware Manual page 118

CHAPTER 5 CLOCKS
Table 5.4-1 Functional Description of Each Bit in the PLL/subclock Control Register (PSCCR)
Bit name
bit15 Unused
to
bit12
bit11 Reserved bit
bit10 SCDS:
Subclock
division selection
bit
bit9 Reserved bit
bit8 CS2:
Multiplication
rate selection bit
Note: PSCCR register is write-only register. Read value is different from writing value. Do not use the RMW instruction
(SETB/CLRB instruction).
102
These bits are not used.
Writing to these bits has no effect to operation.
Read value is always "1".
Always write "0" to this bit.
Read value is always "1".
The division ratio of the subclock is selected.
When "0" is written to this bit, 4 division is selected.
When "1" is written to this bit, 2 division is selected.
Read value is always "1".
This bit is initialized to "0" by all reset causes.
Always write "0" to this bit.
Read value is always "1".
This bit and CS1 and CS0 bits of the clock selection register (CKSCR) determine the PLL
multiplication rate.
CS2 CS1
0 0
0 0
0 1
0 1
1 1
1 1
Read value is always "1".
This bit is initialized to "0" by all reset causes.
Note: When MCS or MCM bit is "0", setting CS2 to CS0 to "111
When CKSCR: CS1 and CS0 is set to "11
Function
CS0 PLL clock multiplication rate
× 1
0
× 2
1
× 3
0
× 4
1
× 6
0
1 Setting disabled
", do not set "1" to this bit.
B
" is prohibited.
B