Pll/Subclock Control Register (Psccr) - Fujitsu F2MCTM-16LX Hardware Manual

5.4

PLL/Subclock Control Register (PSCCR)

PLL/Subclock control register selects the PLL multiplication rate and subclock division
rate. This register is write only. Read value of all bits is set to "1".
Configuration of the PLL/Subclock Control Register (PSCCR)
Figure 5.4-1 shows the configuration of the PLL/Subclock control register (PSCCR). Table 5.4-1 shows the
function of each bit in the PLL/subclock control register (PSCCR).
Figure 5.4-1 Configuration of the PLL/Subclock Control Register (PSCCR)
Address 15
−
0000CF
H
−
W : Write only
X : Undefined
−
: Unused
: Initial value
14 13 12 11 10
− − −
Re- SCDS
served
− − −
W
9 8 Reset value
Re- CS2 XXXX0000
served
W W W
bit8
CS2 Multiplication rate selection bit
0
See the clock selection register
(CKSCR).
1
bit9
Reserved
0 Always write "0" to this bit.
Read value is always "1".
bit10
SCDS Subclock division selection bit
0 4 division
1 2 division
bit11
Reserved
0 Always write "0" to this bit.
Read value is always "1".
CHAPTER 5 CLOCKS
B
Reserved bit
Reserved bit
101