Configuration Of Control Status Register (Csr) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.1

Configuration of Control Status Register (CSR)

This register indicates bus operation, node status, transmit output enable and transmit/
receive status. The lower 8-bit with the control status register (CSR) is prohibited from
executing any bit manipulation instructions (Read-Modify-Write instructions). Only in
the case of HALT bits unchanged (initialization of the macro instructions etc.), there is
no problem even if any bit manipulation instructions is used.
Control Status Register (CSR) (Lower)
Figure 21.4-1 Configuration of the Control Status Register (lower byte)
Address:
CAN1: 007D00
Control Status Register (CSR) (upper)
Figure 21.4-2 Configuration of the Control Status Register (upper byte)
Address:
CAN1: 007D01
7 6
5 4 3 2 1
Re-
TOE NIE
H
served
R/W - - - - R/W W
R/W : Read/Writ
W : Write only
X : Undefined
- : Unused
: Reset value
15 14 13 12 11 10 9
H TS RS NT NS1 NS0
R R - - - R/W R
R/W : Read/Write
R : Read only
X : Undefined
- : Unused
: Reset value
CSR1 (Lower)
0
Reset Vaue
HALT
0 X X X X 0 X 1
B
R/W
bit0
HALT Bus operation styop bit
0 Write: Stop of bus operation is released.
Read:The state of bus operation is not stop mode
1 Write: Stops bus operation
Read: Bus operation in stop mode
bit1
Reserved Reserved bit
0
Always write "0" to this bit.
bit2
NIE Node status transition interrupt enable
0 Node status transition interrupt enabled
1
Node status transition interrupt disabled
bit7
TOE Transmit output enable
0
General-purpose port pin
1 Transmit pin of TX
CSR1 (High)
8
Reset value
0 0 X X X 0 0 0
B
R
bit9 bit8
NS1 NS0 Node status bit
0 0 Error active
0 1
Warning (error active)
1 0 Error passive
Bus off
1 1
bit10
NT Node status transfer flag
0
With node status transfer
1
Without node status reansfer
bit14
RS Reception status bit
0
Message is not received.
1
Massage is being received.
bit15
TS Transfer status bit
0
Message is not transferred.
1
Message is being transferred.
453