Timer Control Status Register (Upper) (Tccsh) - Fujitsu F2MCTM-16LX Hardware Manual

13.3.1

Timer Control Status Register (Upper) (TCCSH)

Timer control status register (upper) selects the count clock and the conditions for
clearing the counter, enables the count operation and interrupt, and checks the
interrupt request flag.
Timer Control Status Register (Upper) (TCCSH)
Address
TCCSH0 : 007943
H
: Read/Write
R/W
: Undefined
X
: Indetermination
: Reset value
Table 13.3-2 Function of Timer Control Status Register (Upper) (TCCSH)
Bit name
bit15 ECKE :
External clock input enable bit
bit14 Undefined bits
to
bit8
Figure 13.3-1 Timer Control Status Register (Upper) (TCCSH)
15 14 13 12 11 10
ECKE
R/W
This bit selects the count clock of the 16-bit free-run timer.
When set to "1": Use the clock inputted from the external pin FRCK0.
When set to "0": Use the internal clock (clock outputted from the
Note:
Set the ECKE bit during stopping of the free-run timer
(TCCSL:STOP=1).
Read: The value is undefined
Write: No effect
9 8
Reset value
0 X X X X X X X
bit15
ECKE External clock input enable bit
0 Use the internal clock (prescaler output).
1 Use the external clock (FRCK0 pin input).
Function
prescaler).
CHAPTER 13 16-Bit I/O TIMER
B
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