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Fujitsu F2MC-8FX Hardware Manual

F2mc-8fx 8-bit microcontroller

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FUJITSU SEMICONDUCTOR

Version 1.0

CONTROLLER MANUAL

2

F

MC-8FX

8-BIT MICROCONTROLLER

MB95170J Series

HARDWARE MANUAL

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Page 1 FUJITSU SEMICONDUCTOR Version 1.0 CONTROLLER MANUAL MC-8FX 8-BIT MICROCONTROLLER MB95170J Series HARDWARE MANUAL...
Page 3 Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Page 5 C Standard Specification as defined by Philips. Sample Programs Fujitsu provides sample programs free of charge to operate the peripheral resources of the F MC-8FX family of microcontrollers. Feel free to use such sample programs to check the operational specifications and usages of Fujitsu microcontrollers.
Page 6 • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. • The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;...
Page 7: Table Of Contents
CONTENTS CHAPTER 1 DESCRIPTION ..................... 1 Feature of MB95170J Series ......................2 Product Lineup of MB95170J Series ....................4 Difference Among Products and Notes on Selecting Products ............7 Block Diagram of MB95170J Series ....................9 Pin Assignment ..........................10 Package Dimension ..........................
Page 8 Clock Oscillator Circuits ........................76 6.10 Overview of Prescaler ........................78 6.11 Configuration of Prescaler ........................ 79 6.12 Operating Explanation of Prescaler ....................80 6.13 Notes on Use of Prescaler ........................ 81 CHAPTER 7 RESET ......................83 Reset Operation ..........................84 Reset Source Register (RSRR) ......................
Page 9 9.10.2 Operations of Port C ........................148 9.11 Port E .............................. 150 9.11.1 Port E Registers ........................152 9.11.2 Operations of Port E ........................153 CHAPTER 10 TIMEBASE TIMER ................... 155 10.1 Overview of Timebase Timer ......................156 10.2 Configuration of Timebase Timer ....................158 10.3 Registers of the Timebase Timer ....................
Page 10 14.5 Explanation of Watch Counter Operations and Setup Procedure Example ........215 14.6 Precautions when Using Watch Counter ..................217 14.7 Sample Programs for Watch Counter ..................... 218 CHAPTER 15 WILD REGISTER ..................219 15.1 Overview of Wild Register ......................220 15.2 Configuration of Wild Register ......................
Page 11 17.6 Interrupts of 16-bit PPG Timer ......................292 17.7 Explanation of 16-bit PPG Timer Operations and Setup Procedure Example ........ 293 17.8 Precautions when Using 16-bit PPG Timer ..................297 17.9 Sample Programs for 16-bit PPG Timer ..................298 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT ............303 18.1 Overview of External Interrupt Circuit .....................
Page 12 21.3.2 UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register (BRSR) ....366 21.4 Operating Description of UART/SIO Dedicated Baud Rate Generator ........... 367 CHAPTER 22 I C ......................369 22.1 Overview of I C ..........................370 22.2 C Configuration ..........................371 22.3 C Channels ..........................
Page 13 24.6.1 Output Waveform during LCD Controller Operation (1/2 Duty) ..........455 24.6.2 Output Waveform during LCD Controller Operation (1/3 Duty) ..........457 24.6.3 Output Waveform during LCD Controller Operation (1/4 Duty) ..........459 24.7 Notes on Use of LCD Controller ..................... 461 CHAPTER 25 LOW-VOLTAGE DETECTION RESET CIRCUIT ........
Page 14 28.4 Starting the Flash Memory Automatic Algorithm ................526 28.5 Checking the Automatic Algorithm Execution Status ..............528 28.5.1 Data Polling Flag (DQ7) ......................530 28.5.2 Toggle Bit Flag (DQ6) ........................ 531 28.5.3 Execution Time-out Flag (DQ5) ....................532 28.5.4 Toggle Bit 2 Flag (DQ2) ......................
Page 15: Chapter 1 Description
CHAPTER 1 DESCRIPTION This chapter explains a feature and a basic specification of the MB95170J series. 1.1 Feature of MB95170J Series 1.2 Product Lineup of MB95170J Series 1.3 Difference Among Products and Notes on Selecting Products 1.4 Block Diagram of MB95170J Series 1.5 Pin Assignment 1.6 Package Dimension 1.7 Pin Description...
Page 16: Feature Of Mb95170J Series
CHAPTER 1 DESCRIPTION Feature of MB95170J Series In addition to a compact instruction set, the MB95170J series is a general-purpose single-chip microcontroller built-in abundant peripheral functions. Feature of MB95170J Series MC-8FX CPU core Instruction system optimized for controllers • Multiplication and division instructions •...
Page 17 Automotive input level / CMOS input level / Hysteresis input level Flash memory security function Protects the content of Flash memory(Flash memory device only) * : Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Rights to use, these components in an C system provided that the system conforms to the I C Standard Specification as defined by Philips.
Page 18: Product Lineup Of Mb95170J Series
CHAPTER 1 DESCRIPTION Product Lineup of MB95170J Series MB95170J series is available in two types. Table 1.2-1 lists the product lineup and Table 1.2-2 lists the CPUs and peripheral functions. Product Lineup of MB95170J Series Table 1.2-1 Product Lineup of MB95170J Series Part Number MB95F176JS MB95F176JW...
Page 19 CHAPTER 1 DESCRIPTION Table 1.2-2 CPU and Peripheral Function of MB95170J Series Item Specification Number of basic instructions: 136 instructions Instruction bit length: 8 bits Instruction length: 1 to 3 bytes CPU function Data bit length: 1, 8, and 16 bits Minimum instruction execution time: 0.1μs (at machine clock 10 MHz) Interrupt processing time:...
Page 20 CHAPTER 1 DESCRIPTION Table 1.2-2 CPU and Peripheral Function of MB95170J Series Item Specification Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Flash memory Number of write/earse cycles (Minimum) : 10000 times Data retention time: 20 years Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Standby Mode...
Page 21: Difference Among Products And Notes On Selecting Products
CHAPTER 1 DESCRIPTION Difference Among Products and Notes on Selecting Products Difference Points among Products and Notes on Selecting a Product Notes on using evaluation products The Evaluation product has not only the functions of the MB95170J series but also those of other products to support software development for multiple series and models of the F MC-8FX family.
Page 22 CHAPTER 1 DESCRIPTION Package and Its Corresponding Product Product MB95F176JS MB95F176JW Package FPT-64P-M23 FPT-64P-M24 : usable × : unusable...
Page 23: Block Diagram Of Mb95170J Series
CHAPTER 1 DESCRIPTION Block Diagram of MB95170J Series Figure 1.4-1 shows the block diagram of all MB95170J series. Block Diagram of All MB95170J Series Figure 1.4-1 Block Diagram of All MB95170J Series MC-8FX CPU Reset control Hardware watchdog RC oscillator X0,X1 Clock control P95/X1A*...
Page 24: Pin Assignment
CHAPTER 1 DESCRIPTION Pin Assignment Pin Assignment of MB95170J Series Figure 1.5-1 Pin Assignment of MB95170J Series (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVss P64/SEG20/EC1 P12/UCK0/TO00 P63/SEG19/TO11 P11/UO0/TO01 P62/SEG18/TO10 P10/UI0/EC0 P61/SEG17...
Page 25: Package Dimension
0~8˚ 0.50±0.20 0.10±0.10 (.020±.008) (.004±.004) "A" (Stand off) 0.60±0.15 (.024±.006) 0.65(.026) 0.32±0.05 0.13(.005) (.013±.002) Dimensions in mm (inches). 2003 FUJITSU LIMITED F64034S-c-1-1 Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...
Page 26 (Stand off) "A" 0.25(.010) 0.50±0.20 (.020±.008) LEAD No. 0.60±0.15 0.50(.020) 0.20±0.05 (.024±.006) 0.08(.003) (.008±.002) Dimensions in mm (inches). 2005 FUJITSU LIMITED F64036S-c-1-1 Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...
Page 27: Pin Description
CHAPTER 1 DESCRIPTION Pin Description Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1. Pin Description Table 1.7-1 Pin Description (1 / 3) Pin no.
Page 28 CHAPTER 1 DESCRIPTION Table 1.7-1 Pin Description (2 / 3) Pin no. circuit Pin name Function LQFP* type* ⎯ Power supply pin (GND) ⎯ Power supply pin ⎯ Capacitor connection pin P95/X1A General-purpose I/O port The pins are shared with sub clock oscillation pin P94/X0A B’...
Page 29 CHAPTER 1 DESCRIPTION Table 1.7-1 Pin Description (3 / 3) Pin no. circuit Pin name Function LQFP* type* P60/S16 General-purpose I/O port The pins are shared with LCDC SEG output. P61/S17 P62/S18/TO10 General-purpose I/O port The pins are shared with LCDC SEG output and 8/16-bit compound timer ch.1 output P63/S19/TO11 (TO10, TO11) General-purpose I/O port...
Page 30 CHAPTER 1 DESCRIPTION *1 : FPT-64P-M23 , FPT-64P-M24 *2 : For the I/O circuit type, refer to “1.8 I/O Circuit Type”.
Page 31: I/O Circuit Type
CHAPTER 1 DESCRIPTION I/O Circuit Type Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Type" column of Table 1.8-1 corresponds to the one in the "I/O circuit type" column of Table 1.7-1. I/O Circuit Type Table 1.8-1 I/O Circuit Type (1 / 3) Type Circuit Remarks...
Page 32 CHAPTER 1 DESCRIPTION Table 1.8-1 I/O Circuit Type (2 / 3) Type Circuit Remarks • CMOS output • Hysteresis input P-ch Digital output • Automotive input Digital output N-ch H’ Hysteresis input Automotive input Standby con- • N-ch open drain output •...
Page 33 CHAPTER 1 DESCRIPTION Table 1.8-1 I/O Circuit Type (3 / 3) Type Circuit Remarks • CMOS output • LCD output P-ch Digital output • CMOS input • Hysteresis input Digital output N-ch • Automotive input LCD output CMOS input Hysteresis input Automotive input LCD control Standby control...
Page 34 CHAPTER 1 DESCRIPTION...
Page 35: Chapter 2 Handling Devices
CHAPTER 2 HANDLING DEVICES This chapter gives notes on using. 2.1 Device Handling Precautions...
Page 36: Device Handling Precautions
CHAPTER 2 HANDLING DEVICES Device Handling Precautions This section summarizes the precautions on the device's power supply voltage and pin treatment. Device Handling Precautions Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than V or lower than V is applied to input and...
Page 37 CHAPTER 2 HANDLING DEVICES Pin Connection Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins.
Page 38 CHAPTER 2 HANDLING DEVICES...
Page 39: Chapter 3 Memory Space
CHAPTER 3 MEMORY SPACE This chapter describes memory space. 3.1 Memory Space 3.2 Memory Map...
Page 40: Memory Space
CHAPTER 3 MEMORY SPACE Memory Space The memory space on the F MC-8FX family is 64 K bytes, divided into I/O, extended I/O, data, and program areas. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Configuration of Memory Space I/O area (addresses: 0000 to 007F...
Page 41 CHAPTER 3 MEMORY SPACE Configuration of Memory Space For Specific Usage General-purpose Register Area (Addresses: 0100 to 01FF • This area contains the auxiliary registers used for 8-bit arithmetic or transfer operations. • As the area is allocated as part of the RAM area, it can also be used as ordinary RAM. •...
Page 42: Memory Map
CHAPTER 3 MEMORY SPACE Memory Map Figure 3.2-1 Memory Map 0000 I/O area Direct addressing area 0080 0100 Register banks Extended direct addressing area (General-purpose register area) 0200 Address #1 Access prohibited 0F00 Extended I/O area Address #2 Program area FFC0 FFFF Vector table area...
Page 43: Chapter 4 Memory Access Mode
CHAPTER 4 MEMORY ACCESS MODE This chapter describes the memory access mode. 4.1 Memory Access Mode...
Page 44: Memory Access Mode
CHAPTER 4 MEMORY ACCESS MODE Memory Access Mode The memory access mode supported by the MB95170J series is only single-chip mode. Single-chip Mode Single-chip mode uses only internal RAM and ROM without using an external bus access. Mode data Mode data is used to determine the memory access mode of the CPU. The mode data address is fixed as FFFD (The value of FFFC can be any value).
Page 45: Chapter 5 Cpu
CHAPTER 5 This chapter describes functions and operations of the CPU. 5.1 Dedicated Registers 5.2 General-purpose Registers 5.3 Placement of 16-bit Data in Memory...
Page 46: Dedicated Registers
CHAPTER 5 CPU Dedicated Registers The CPU has its dedicated registers: the program counter (PC), two arithmetic registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS) register. Each of the registers is 16 bits long. The PS register consists of the register bank pointer (RP), direct pointer (DP), and condition code register (CCR).
Page 47 CHAPTER 5 CPU Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit register for arithmetic operation. It is used to perform arithmetic operations with the data in the accumulator (A). The data in the temporary accumulator is handled as word data for word-length (16-bit) operations with the accumulator (A) and as byte data for byte-length (8-bit) operations.
Page 48: Register Bank Pointer (Rp)
CHAPTER 5 CPU 5.1.1 Register Bank Pointer (RP) The register bank pointer (RP) in bits 15 to 11 of the program status (PS) register contains the address of the general-purpose register bank that is currently in use and is translated into a real address when general-purpose register addressing is used. Configuration of Register Bank Pointer (RP) Figure 5.1-2 shows the configuration of the register bank pointer.
Page 49: Direct Bank Pointer (Dp)
CHAPTER 5 CPU 5.1.2 Direct Bank Pointer (DP) The direct bank pointer (DP) in bits 10 to 8 of the program status (PS) register specifies the area to be accessed by direct addressing. Configuration of Direct Bank Pointer (DP) Figure 5.1-4 shows the configuration of the direct bank pointer. Figure 5.1-4 Configuration of Direct Bank Pointer DP Initial value...
Page 50 CHAPTER 5 CPU Table 5.1-2 Direct Address Instruction List Applicable Instruction CLRB dir:bit SETB dir:bit BBC dir:bit,rel BBS dir:bit,rel MOV A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#imm CMP dir,#imm MOVW A,dir MOVW dir,A...
Page 51: Condition Code Register (Ccr)
CHAPTER 5 CPU 5.1.3 Condition Code Register (CCR) The condition code register (CCR) in the lower eight bits of the program status (PS) register consists of the bits (H, N, Z, V, and C) containing information about the arithmetic result or transfer data and the bits (I, IL1, and IL0) used to control the acceptance of interrupt requests.
Page 52 CHAPTER 5 CPU Carry flag (C) This flag is set to "1" when a carry from bit 7 or a borrow to bit 7 occurs as the result of an operation. Otherwise, the flag is set to "0". When a shift instruction is executed, the flag is set to the shift-out value. Figure 5.1-6 shows how the carry flag is updated by a shift instruction.
Page 53: General-Purpose Registers
CHAPTER 5 CPU General-purpose Registers The general-purpose registers are memory blocks consisting of eight 8-bit registers per bank. A total of up to 32 register banks can be used. The register bank pointer (RP) is used to specify the register bank. Register banks are useful for interrupt handling, vector call processing, and subroutine calls.
Page 54 CHAPTER 5 CPU Features of General-purpose Registers The general-purpose registers have the following features: • High-speed access to RAM using short instructions (general-purpose register addressing). • Blocks of register banks facilitating data backup and division by function unit. General-purpose register banks can be allocated exclusively for specific interrupt service routines or vector call (CALLV #0 to #7) processing routines.
Page 55: Placement Of 16-Bit Data In Memory
CHAPTER 5 CPU Placement of 16-bit Data in Memory This section describes how 16-bit data is stored in memory. Placement of 16-bit Data in Memory State of 16-bit data stored in RAM When you write 16-bit data to memory, the upper byte of the data is stored at a smaller address and the lower byte is stored at the next address.
Page 56 CHAPTER 5 CPU...
Page 57: Chapter 6 Clock Controller
CHAPTER 6 CLOCK CONTROLLER This chapter describes the functions and operations of the clock controller. 6.1 Overview of Clock Controller 6.2 Oscillation Stabilization Wait Time 6.3 System Clock Control Register (SYCC) 6.4 PLL Control Register (PLLC) 6.5 Oscillation Stabilization Wait Time Setting Register (WATR) 6.6 Standby Control Register (STBC) 6.7 Clock Modes 6.8 Operations in Low-power Consumption Modes (Standby Modes)
Page 58: Overview Of Clock Controller
CHAPTER 6 CLOCK CONTROLLER Overview of Clock Controller The F MC-8FX family has a built-in clock controller that optimizes its power consumption. It includes two- system clock product supporting both of the main clock and subclock and single system clock product supporting only the main clock. The clock controller enables/disables clock oscillation, enables/disables the supply of clock signals to the internal circuitry, selects the clock source, and controls the PLL and frequency divider circuits.
Page 59 CHAPTER 6 CLOCK CONTROLLER Block Diagram of the Clock Controller Figure 6.1-1 shows the block diagram of the clock controller. Figure 6.1-1 Clock Controller Block Diagram PLL controller register (PLLC) Standby control register (STBC) SPL SRST TMD MPEN MPMC1 MPMC0MPRDY Stop signal Sleep signal Clock for watch...
Page 60 CHAPTER 6 CLOCK CONTROLLER The clock controller consists of the following blocks: Main clock oscillator circuit This block is the oscillator circuit for the main clock. Subclock oscillator circuit (Two-system clock product) This block is the oscillator circuit for the subclock. Main PLL oscillator circuit This block is the oscillator circuit for the main PLL.
Page 61: Clock Modes
CHAPTER 6 CLOCK CONTROLLER Clock Modes There are three clock modes available: main clock mode, main PLL clock mode and subclock mode. Table 6.1-1 shows the relationships between the clock modes and the machine clock (operating clock for the CPU and peripheral resources). Table 6.1-1 Clock Modes and Machine Clock Selection Clock Mode Machine Clock...
Page 62 CHAPTER 6 CLOCK CONTROLLER Standby Modes The clock controller selects whether to enable or disable clock oscillation and clock supply to internal circuitry depending on each standby mode. With the exception of timebase timer mode and watch mode, the standby mode can be set independently of the clock mode. Table 6.1-3 shows the relationships between standby modes and clock supply states.
Page 63 CHAPTER 6 CLOCK CONTROLLER Combinations of Clock Mode and Standby Mode Table 6.1-4 lists the combinations of clock mode and standby mode and their respective operating states of internal circuits. Table 6.1-4 Combinations of Standby Mode and Clock Mode and Internal Operating States Watch (Two- Timebase Sleep...
Page 64: Oscillation Stabilization Wait Time
CHAPTER 6 CLOCK CONTROLLER Oscillation Stabilization Wait Time The oscillation stabilization wait time is the time after the oscillator circuit stops oscillation until the oscillator resumes its stable oscillation at its natural frequency. The clock controller obtains the oscillation stabilization wait time by counting a set number of oscillation clock cycles to prevent clock supply to internal circuits.
Page 65 CHAPTER 6 CLOCK CONTROLLER the PLL oscillation stabilization wait time to elapse after a request for state transition from PLL oscillation stopped state to oscillation start is generated via an interrupt in standby mode or a change of clock mode by software.
Page 66: System Clock Control Register (Sycc)
CHAPTER 6 CLOCK CONTROLLER System Clock Control Register (SYCC) The system clock control register (SYCC) is used to indicate and switch the current clock mode, select the machine clock divide ratio, and control subclock oscillation in main clock mode and main PLL clock mode. Configuration of System Clock Control Register (SYCC) Figure 6.3-1 Configuration of System Clock Control Register (SYCC)
Page 67 CHAPTER 6 CLOCK CONTROLLER Table 6.3-1 Functions of Bits in System Clock Control Register (SYCC) Bit name Function Indicate the current clock mode. SCM1, SCM0: When set to "00": the bits indicate subclock mode. bit7 Clock mode monitor When set to "10": the bit indicate main clock mode. bit6 bits When set to "11": the bit indicate main PLL clock mode.
Page 68: Pll Control Register (Pllc)
CHAPTER 6 CLOCK CONTROLLER PLL Control Register (PLLC) The PLL control register (PLLC) controls the main PLL clock. Configuration of PLL Control Register (PLLC) Figure 6.4-1 Configuration of PLL Control Register (PLLC) Address Initial value bit7 bit6 bit5 bit3 bit2 bit1 bit4 bit0...
Page 69 CHAPTER 6 CLOCK CONTROLLER Table 6.4-1 Functions of Bits in PLL Control Register (PLLC) Bit name Function Enables or disables the oscillation of the main PLL clock in main clock mode or timebase timer mode. MPEN: When set to "1": the bit enables main PLL clock oscillation. bit7 Main PLL clock When set to "0": the bit disables main PLL clock oscillation.
Page 70: Oscillation Stabilization Wait Time Setting Register (Watr)
CHAPTER 6 CLOCK CONTROLLER Oscillation Stabilization Wait Time Setting Register (WATR) This register is used to set the oscillation stabilization wait time. Configuration of Oscillation Stabilization Wait Time Setting Register (WATR) Figure 6.5-1 Configuration of Oscillation Stabilization Wait Time Setting Register (WATR) Initial value Address Bit7...
Page 71 CHAPTER 6 CLOCK CONTROLLER Table 6.5-1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register (WATR) (1 / 2) Bit name Function Set the subclock oscillation stabilization wait time. Number of Subclock F = 32.768 kHz SWT3 SWT2 SWT1 SWT0 Cycles 1111 About...
Page 72 CHAPTER 6 CLOCK CONTROLLER Table 6.5-1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register (WATR) (2 / 2) Bit name Function Set the main clock oscillation stabilization wait time. MWT3 MWT2 MWT1 Number of Main clock F = 4 MHz MWT0 Cycles 1111...
Page 73 CHAPTER 6 CLOCK CONTROLLER...
Page 74: Standby Control Register (Stbc)
CHAPTER 6 CLOCK CONTROLLER Standby Control Register (STBC) The standby control register (STBC) is used to control transition from the RUN state to sleep mode, stop mode, timebase timer mode, or watch mode, set the pin state in stop mode, timebase timer mode, and watch mode, and to control the generation of software resets.
Page 75 CHAPTER 6 CLOCK CONTROLLER Table 6.6-1 Functions of Bits in Standby Control Register (STBC) Bit Name Function Sets transition to stop mode. When set to "0": the bit is meaningless. STP: When set to "1": the bit causes transition to stop mode. bit7 Stop bit •...
Page 76 CHAPTER 6 CLOCK CONTROLLER Notes: • Set the standby mode after making sure that the transition to clock mode has been completed by comparing the values of the clock mode monitor bits (SYCC:SCM1,0) and clock mode setting bits (SYCC:SCS1,0) in the system clock control register.
Page 77: Clock Modes
CHAPTER 6 CLOCK CONTROLLER Clock Modes The clock modes available are: main clock mode, subclock mode and main PLL clock mode. Mode switching takes place according to the settings in the system clock control register (SYCC). Subclock mode is not supported by single system clock product. Operations in Main Clock Mode Main clock mode uses the main clock as the machine clock for the CPU and peripheral resources.
Page 78 CHAPTER 6 CLOCK CONTROLLER Clock Mode State Transition Diagram The clock modes available are: main clock mode, main PLL clock mode and subclock mode. The device can switch between these modes according to the settings in the system clock control register (SYCC). Figure 6.7-1 Clock Mode State Transition Diagram (Two-system Clock Product) Power on Reset occurs in each state.
Page 79 CHAPTER 6 CLOCK CONTROLLER Figure 6.7-2 Clock Mode State Transition Diagram (Single System Clock Product) Power on Reset occurs in each state. Reset state <1> <2> Main clock oscillation stabilization wait time Main PLL Main clock mode clock mode Main PLL clock oscillation stabiliza- tion wait time...
Page 80 CHAPTER 6 CLOCK CONTROLLER Table 6.7-1 Clock Mode State Transition Table Current Next State Description State After a reset, the device waits for the main clock oscillation stabilization wait time to elapse <1> and enters main clock mode. Reset state Main clock If the reset is a watchdog reset, software reset, or external reset caused in main clock mode or main PLL clock mode, however, the device does not wait for the main clock oscillation...
Page 81: Operations In Low-Power Consumption Modes (Standby Modes)
CHAPTER 6 CLOCK CONTROLLER Operations in Low-power Consumption Modes (Standby Modes) The standby modes available are: sleep mode, stop mode, timebase timer mode, and watch mode. Overview of Transitions to and from Standby Mode The standby modes available are: sleep mode, stop mode, timebase timer mode, and watch mode. The device enters standby mode according to the settings in the standby control register (STBC).
Page 82: Notes On Using Standby Mode
CHAPTER 6 CLOCK CONTROLLER 6.8.1 Notes on Using Standby Mode Even if the standby control register (STBC) sets standby mode, transition to the standby mode does not take place when an interrupt request has been issued from a peripheral resource. When the device returns from standby mode to the normal operating state in response to an interrupt, the operation that follows varies depending on whether the interrupt request is accepted or not.
Page 83 CHAPTER 6 CLOCK CONTROLLER Standby Mode State Transition Diagram Figure 6.8-1 and Figure 6.8-2 are standby mode state transition diagrams. Figure 6.8-1 Standby Mode State Transition Diagram (Two-system Clock Product) Power on Reset state Reset occurs in each state. <2> <1>...
Page 84 CHAPTER 6 CLOCK CONTROLLER Figure 6.8-2 Standby Mode State Transition Diagram (Single System Clock Product) Power on Reset state Reset occurs in each state. <2> <1> Main clock oscillation stabilization wait time Normal (RUN) state Stop mode Main clock/main PLL clock oscillation stabilization wait time Main PLL clock...
Page 85 CHAPTER 6 CLOCK CONTROLLER Table 6.8-1 State Transition Diagram (Transitions to and from Standby Modes) State Transition Description After a reset, the device enters main clock mode. If the reset is a power-on reset, the device always waits for the main clock oscillation stabilization <1>...
Page 86: Sleep Mode
CHAPTER 6 CLOCK CONTROLLER 6.8.2 Sleep Mode Sleep mode stops the operations of the CPU and watchdog timer. Operations in Sleep Mode Sleep mode stops the operating clock for the CPU and watchdog timer. In this mode, the CPU stops while retaining the contents of registers and RAM that exist immediately before the transition to sleep mode, but the peripheral resources except the watchdog timer continue operating.
Page 87: Stop Mode
CHAPTER 6 CLOCK CONTROLLER 6.8.3 Stop Mode Stop mode stops the main clock. Operations in Stop Mode Stop mode stops the main clock. In this mode, the device stops all the functions except external interrupt and low-voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to stop mode.
Page 88: Timebase Timer Mode
CHAPTER 6 CLOCK CONTROLLER 6.8.4 Timebase Timer Mode Timebase timer mode allows only the main clock oscillation, subclock oscillation, timebase timer, and watch prescaler to work. The operating clock for the CPU and peripheral resources is stopped in this mode. Operations in Timebase Timer Mode In timebase timer mode, main clock supply is stopped except for the timebase timer.
Page 89: Watch Mode
CHAPTER 6 CLOCK CONTROLLER 6.8.5 Watch Mode Watch mode allows only the subclock and watch prescaler to work. The operating clock for the CPU and peripheral resources is stopped in this mode. Operations in Watch Mode In watch mode, the operating clock for the CPU and peripheral resources is stopped. The device stops all the functions except the watch prescaler, watch counter, external interrupt, and low-voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to watch mode.
Page 90: Clock Oscillator Circuits
CHAPTER 6 CLOCK CONTROLLER Clock Oscillator Circuits The clock oscillator circuit generates an internal clock with an oscillator connected to or a clock signal input to the clock oscillation pin. Clock Oscillator Circuit Using crystal and ceramic oscillators Connect crystal and ceramic oscillators as shown in Figure 6.9-1. Figure 6.9-1 Sample Connections of Crystal and Ceramic Oscillators Two-system clock product Single system clock product...
Page 91 CHAPTER 6 CLOCK CONTROLLER Note: If you use only the main clock without using subclock oscillation on a two-system clock product and it enters subclock mode for some reason, there is no solution to recovering its operation as there is no clock supply available.
Page 92: Overview Of Prescaler
CHAPTER 6 CLOCK CONTROLLER 6.10 Overview of Prescaler The prescaler generates the count clock source for various peripheral resources from the machine clock (MCLK) and the count clock output from the time-base timer. Prescaler The prescaler generates the count clock source for various peripheral resources from the machine clock (MCLK) that drives the CPU and the count clock (2 or 2 ) output from of the time-base timer.
Page 93: Configuration Of Prescaler
CHAPTER 6 CLOCK CONTROLLER 6.11 Configuration of Prescaler Figure 6.11-1 is a block diagram of the prescaler. Prescaler Block Diagram Figure 6.11-1 Prescaler Block Diagram Prescaler 2/MCLK 4/MCLK Count Counter value 8/MCLK clock MCLK (machine clock) 5-bit source Output 16/MCLK counter control circuit 32/MCLK...
Page 94: Operating Explanation Of Prescaler
CHAPTER 6 CLOCK CONTROLLER 6.12 Operating Explanation of Prescaler The prescaler generates count clock sources to individual peripheral resources. Operations of Prescaler The prescaler generates count clock sources from the frequency-divided version of the machine clock (MCLK) and buffered signals from the timebase timer (2 ) and supplies them to individual peripheral resources.
Page 95: Notes On Use Of Prescaler
CHAPTER 6 CLOCK CONTROLLER 6.13 Notes on Use of Prescaler This section gives notes on using the prescaler. The prescaler uses the machine clock and timebase timer clock and operates continuously while these clocks are running. Accordingly, the operations of individual peripheral resources immediately after they are activated may involve an error of up to one cycle of the clock source captured by the resource, depending on the prescaler output value.
Page 96 CHAPTER 6 CLOCK CONTROLLER...
Page 97: Chapter 7 Reset
CHAPTER 7 RESET This section describes the reset operation. 7.1 Reset Operation 7.2 Reset Source Register (RSRR)
Page 98: Reset Operation
CHAPTER 7 RESET Reset Operation When a reset factor occurs, the CPU stops the current execution immediately and enters the reset release wait state. When the device is released from the reset, the CPU reads mode data and the reset vector from internal ROM (mode fetch). When the power is turned on or when the device is released from a reset in subclock mode or stop mode, the CPU performs mode fetch after the oscillation stabilization wait time has passed.
Page 99 CHAPTER 7 RESET Power-on reset/low-voltage detection reset A power-on reset is generated when the power is turned on. Some 5-V products have a low-voltage detection reset circuit integrated. The low-voltage detection reset circuit generates a reset if the power supply voltage falls below a predetermined level.
Page 100 CHAPTER 7 RESET Overview of Reset Operation Figure 7.1-1 Reset Operation Flow Power-on reset/ External reset input low-voltage detection Software reset reset Watchdog reset Suppress resets during RAM access Suppress resets during RAM access During reset In subclock mode, or stop mode Subclock mode During operation in sub-PLL clock mode...
Page 101 CHAPTER 7 RESET Note: Connect a pull-up resistor to those pins which remain at high impedance during a reset to prevent the devices the pins from malfunctioning.
Page 102: Reset Source Register (Rsrr)
CHAPTER 7 RESET Reset Source Register (RSRR) The reset source register indicates the source or factor causing a reset that has been generated. Configuration of Reset Source Register (RSRR) Figure 7.2-1 Reset Source Register (RSRR) Address Initial value Bit7 Bit6 Bit5 Bit4 Bit3...
Page 103: Chapter 7 Reset
CHAPTER 7 RESET Table 7.2-1 Functions of Bits in Reset Source Register (RSRR) Bit Name Function The value read is always 0. bit7 Unused bits These bits are read-only. Any value written is meaningless. This bit is set to "1" to indicate that a hardware watchdog reset has occurred. HWDR: Otherwise, the bit retains the value existing before the reset occurred.
Page 104 CHAPTER 7 RESET...
Page 105: Chapter 8 Interrupts
CHAPTER 8 INTERRUPTS This chapter explains the interrupts. 8.1 Interrupts...
Page 106: Interrupts
CHAPTER 8 INTERRUPTS Interrupts This section explains the interrupts. Overview of Interrupts The F MC-8FX family has 24 interrupt request input lines corresponding to peripheral resources, for each of which an interrupt level can be set independently. When a peripheral resource generates an interrupt request, the interrupt request is output to the interrupt controller.
Page 107 CHAPTER 8 INTERRUPTS Table 8.1-1 Interrupt Requests and Interrupt Vectors Vector Table Address Priority for Equal-level Interrupt Bit in Interrupt Level Interrupt Request Requests Setting Register Upper Lower (Generated Simultaneously) FFFA FFFB IRQ0 L00 [1:0] Highest FFF8 FFF9 IRQ1 L01 [1:0] FFF6 FFF7 IRQ2...
Page 108: Interrupt Level Setting Registers (Ilr0 To Ilr5)
CHAPTER 8 INTERRUPTS 8.1.1 Interrupt Level Setting Registers (ILR0 to ILR5) The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of bits assigned for the interrupt requests from different peripheral resources. Each pair of bits (interrupt level setting bits as two-bit data) sets each interrupt level. Configuration of Interrupt Level Setting Registers (ILR0 to ILR5) Figure 8.1-1 Configuration of Interrupt Level Setting Registers Register...
Page 109: Interrupt Processing
CHAPTER 8 INTERRUPTS 8.1.2 Interrupt Processing When an interrupt request is generated by a peripheral resource, the interrupt controller passes the interrupt level to the CPU. When the CPU is ready to accept interrupts, it temporarily halts the program currently being executed and executes an interrupt service routine.
Page 110 CHAPTER 8 INTERRUPTS (1) Any interrupt request is disabled immediately after a reset. In the peripheral resource initialization program, initialize those peripheral resources which generate interrupts and set their interrupt levels in their respective interrupt level setting registers (ILR0 to ILR5) before starting operating the peripheral resources.
Page 111: Nested Interrupts
CHAPTER 8 INTERRUPTS 8.1.3 Nested Interrupts You can set different interrupt levels for two or more interrupt requests from peripheral resources in the interrupt level setting registers (ILR0 to ILR5) to process the nested interrupts. Nested Interrupts If an interrupt request of higher-priority interrupt level occurs while an interrupt service routine is being executed, the CPU halts processing of the current interrupt and accepts the higher-priority interrupt request.
Page 112: Interrupt Processing Time
CHAPTER 8 INTERRUPTS 8.1.4 Interrupt Processing Time The time between an interrupt request being generated and control being passed to the interrupt processing routine is equal to the sum of the time until the currently executing instruction completes and the interrupt handling time (time required to initiate interrupt processing).
Page 113: Stack Operations During Interrupt Processing
CHAPTER 8 INTERRUPTS 8.1.5 Stack Operations During Interrupt Processing This section describes how registers are saved and restored during interrupt processing. Stack Operation at the Start of Interrupt Processing Once the CPU accepts an interrupt, it automatically saves the current program counter (PC) and program status (PS) values onto a stack.
Page 114: Interrupt Processing Stack Area
CHAPTER 8 INTERRUPTS 8.1.6 Interrupt Processing Stack Area The stack area in RAM is used for interrupt processing. The stack pointer (SP) contains the start address of the stack area. Interrupt Processing Stack Area The stack area is also used to save and restore the program counter (PC) when subroutine call (CALL) or vector call (CALLV) instructions are executed and to temporarily save and restore the registers via the PUSHW and POPW instructions.
Page 115: Chapter 9 I/O Port
CHAPTER 9 I/O PORT This chapter describes the functions and operations of the I/O ports. 9.1 Overview of I/O Ports 9.2 Port 0 9.3 Port 1 9.4 Port 4 9.5 Port 5 9.6 Port 6 9.7 Port 9 9.8 Port A 9.9 Port B 9.10 Port C 9.11 Port E...
Page 116: Overview Of I/O Ports
CHAPTER 9 I/O PORT Overview of I/O Ports I/O ports are used to control general-purpose I/O pins. Overview of I/O Ports The I/O port has functions to output data from the CPU and load inputted signals into the CPU, via the port data register (PDR).
Page 117 CHAPTER 9 I/O PORT R/W: Readable/writable (Read value is the same as the write value.) R, RM/W: Readable/writable (Read value is different from write value, write value is read by read-modify-write instruction.)
Page 118: Port 0
CHAPTER 9 I/O PORT Port 0 Port 0 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 0 Configuration Port 0 is made up of the following elements. •...
Page 119 CHAPTER 9 I/O PORT Block Diagram of Port 0 Figure 9.2-1 Block Diagram of Port 0 (Except P06 and P07) A/D analog input Peripheral function input Peripheral function input enable Hysteresis Pull-up PDR read Automotive PDR write At bit operation instruction DDR read DDR write Stop, watch (SPL=1)
Page 120: Port 0 Registers
CHAPTER 9 I/O PORT 9.2.1 Port 0 Registers This section describes the port 0 registers. Port 0 Register Function Table 9.2-2 lists the port 0 register functions. Table 9.2-2 Port 0 Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 121: Operations Of Port 0
CHAPTER 9 I/O PORT 9.2.2 Operations of Port 0 This section describes the operations of port 0. Operations of Port 0 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 122 CHAPTER 9 I/O PORT Operation in stop mode and watch mode • If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the DDR value.
Page 123: Port 1
CHAPTER 9 I/O PORT Port 1 Port 1 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 1 Configuration Port 1 is made up of the following elements. •...
Page 124 CHAPTER 9 I/O PORT Block Diagram of Port 1 Figure 9.3-1 Block Diagram of Port1 (For P10) Peripheral function input Peripheral function input enable Hysteresis Pull-up Automotive PDR read CMOS PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1) PUL read PUL write...
Page 125 CHAPTER 9 I/O PORT Figure 9.3-3 Block Diagram of Port1 (For P13 and P14)) Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis PDR read Automotive PDR write Only P13 is selectable. In bit operation instruction DDR read DDR write Stop, Watch (SPL=1)
Page 126: Port 1 Registers
CHAPTER 9 I/O PORT 9.3.1 Port 1 Registers This section describes the port 1 registers. Port 1 Register Function Table 9.3-2 lists the port 1 register functions. Table 9.3-2 Port 1 Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 127: Operations Of Port 1
CHAPTER 9 I/O PORT 9.3.2 Operations of Port 1 This section describes the operations of port 1. Operations of Port 1 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 128 CHAPTER 9 I/O PORT Operation in stop mode and watch mode • If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the DDR value.
Page 129: Port 4
CHAPTER 9 I/O PORT Port 4 Port 4 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 4 Configuration Port 4 is made up of the following elements. •...
Page 130 CHAPTER 9 I/O PORT Block Diagram of Port 4 Figure 9.4-1 Block Diagram of Port 4 Peripheral function output enable Peripheral function output Hysteresis PDR read Automotive PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1) ILSR2 read ILSR2 ILSR2 write...
Page 131: Port 4 Registers
CHAPTER 9 I/O PORT 9.4.1 Port 4 Registers This section describes the port 4 registers. Port 4 Register Function "Table 9.4-2 Port 4 Register Function" lists the port 4 register functions. Table 9.4-2 Port 4 Register Function Register Data Read Read read-modify-write Write name...
Page 132: Operations Of Port 4
CHAPTER 9 I/O PORT 9.4.2 Operations of Port 4 This section describes the operations of port 4. Operations of Port 4 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 133 CHAPTER 9 I/O PORT Table 9.4-4 shows the pin states of the port. Table 9.4-4 Pin State of Port 4 Normal operation Operating Sleep Stop (SPL=1) At reset state Stop (SPL=0) Watch (SPL=1) Watch (SPL=0) Hi-Z I/O port/ Hi-Z Pin state (the pull-up setting is enabled) analog input Input disabled*...
Page 134: Port 5
CHAPTER 9 I/O PORT Port 5 Port 5 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 5 Configuration Port 5 is made up of the following elements. •...
Page 135 CHAPTER 9 I/O PORT Block Diagram of Port 5 Figure 9.5-1 Block Diagram of Port 5 Peripheral function input Peripheral function input enable Peripheral function output enable Automotive Peripheral function output Hysteresis PDR read CMOS PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1)
Page 136: Port 5 Registers
CHAPTER 9 I/O PORT 9.5.1 Port 5 Registers This section describes the port 5 registers. Port 5 Register Function Table 9.7-2 lists the port 5 register functions. Table 9.5-2 Port 5 Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 137: Operations Of Port 5
CHAPTER 9 I/O PORT 9.5.2 Operations of Port 5 This section describes the operations of port 5. Operations of Port 5 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 138 CHAPTER 9 I/O PORT Operation in stop mode and watch mode • If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the DDR value.
Page 139: Port 6
CHAPTER 9 I/O PORT Port 6 Port 6 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 6 Configuration Port 6 is made up of the following elements. •...
Page 140 CHAPTER 9 I/O PORT Block Diagram of Port 6 Figure 9.6-1 Block Diagram of Port 6 LCD output Peripheral function input Peripheral function input enable LCD output enable Peripheral function output enable Peripheral function output Hysteresis PDR read Automotive PDR write In bit operation instruction DDR read DDR write...
Page 141: Port 6 Registers
CHAPTER 9 I/O PORT 9.6.1 Port 6 Registers This section describes the port 6 registers. Port 6 Register Function Table 9.6-2 lists the port 6 register functions. Table 9.6-2 Port 6 Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 142: Operations Of Port 6
CHAPTER 9 I/O PORT 9.6.2 Operations of Port 6 This section describes the operations of port 6. Operations of Port 6 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 143 CHAPTER 9 I/O PORT Operation in stop mode and watch mode • If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the DDR value.
Page 144: Port 9
CHAPTER 9 I/O PORT Port 9 Port 9 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port 9 Configuration Port 9 is made up of the following elements. •...
Page 145 CHAPTER 9 I/O PORT Block Diagram of Port 9 Figure 9.7-1 Block Diagram of Port 9 Peripheral function input Peripheral function output enable Peripheral function output Hysteresis Pull-up Automotive PDR read Selectalbe only P94 and P95 PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1)
Page 146: Port 9 Registers
CHAPTER 9 I/O PORT 9.7.1 Port 9 Registers This section describes the port 9 registers. Port 9 Register Function Table 9.7-2 lists the port 9 register functions. Table 9.7-2 Port 9 Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 147: Operations Of Port 9
CHAPTER 9 I/O PORT 9.7.2 Operations of Port 9 This section describes the operations of port 9. Operations of Port 9 Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 148 CHAPTER 9 I/O PORT Operation of the input level selection register • Writing "1" to the bit6 of ILSR2 changes Port 9 from the hysteresis input level to the automotive input level. When the bit6 of ILSR2 is "0", it should be the hysteresis input level. Table 9.7-4 shows the pin states of the port Table 9.7-4 Pin State of Port 9 Normal operation...
Page 149: Port A
CHAPTER 9 I/O PORT Port A Port A is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port A Configuration Port A is made up of the following elements. •...
Page 150 CHAPTER 9 I/O PORT Block Diagram of Port A Figure 9.8-1 Block Diagram of Port A LCD output LCD enable Hysteresis PDR read Automotive PDR write At bit operation instruction DDR read DDR write Stop, watch (SPL=1) ILSR2 read ILSR2 ILSR2 write...
Page 151: Port A Registers
CHAPTER 9 I/O PORT 9.8.1 Port A Registers This section describes the port A registers. Port A Register Function Table 9.8-2 lists the port A register functions. Table 9.8-2 Port A Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 152: Operations Of Port A
CHAPTER 9 I/O PORT 9.8.2 Operations of Port A This section describes the operations of port A. Operations of Port A Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 153 CHAPTER 9 I/O PORT Table 9.8-4 shows the pin states of the port Table 9.8-4 Pin State of Port A Normal operation Operating Sleep Stop (SPL=1) At reset state Stop (SPL=0) Watch (SPL=1) Watch (SPL=0) I/O port/peripheral Hi-Z Hi-Z Pin state function I/O Input cutoff Input disabled*...
Page 154: Port B
CHAPTER 9 I/O PORT Port B Port B is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port B Configuration Port B is made up of the following elements. •...
Page 155 CHAPTER 9 I/O PORT Block Diagram of Port B Figure 9.9-1 Block Diagram of Port B LCD output Peripheral function input LCD enable Peripheral function input enable Peripheral function output Peripheral function output enable Hysteresis PDR read Automotive PDR write At bit operation instruction Selectable only PB0 DDR read...
Page 156: Port B Registers
CHAPTER 9 I/O PORT 9.9.1 Port B Registers This section describes the port B registers. Port B Register Function Table 9.9-2 lists the port B register functions. Table 9.9-2 Port B Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 157: Operations Of Port B
CHAPTER 9 I/O PORT 9.9.2 Operations of Port B This section describes the operations of port B. Operations of Port B Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 158 CHAPTER 9 I/O PORT • As with input port, when a pin jointly used for LCD is used as another peripheral function input,configure it as an input port. • When a PDR register is read, the value of the pin can be read, regardless of whether the peripheral function uses an input pin.
Page 159: Port C
CHAPTER 9 I/O PORT 9.10 Port C Port C is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port C Configuration Port C is made up of the following elements. •...
Page 160 CHAPTER 9 I/O PORT Block Diagram of Port C Figure 9.10-1 Block Diagram of Port C LCD output LCD enable Peripheral function input Peripheral function input enable Hysteresis PDR read Automotive PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1) ILSR3 read ILSR3...
Page 161: Port C Registers
CHAPTER 9 I/O PORT 9.10.1 Port C Registers This section describes the port C registers. Port C Register Function Table 9.10-2 lists the port C register functions. Table 9.10-2 Port C Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 162: Operations Of Port C
CHAPTER 9 I/O PORT 9.10.2 Operations of Port C This section describes the operations of port C. Operations of Port C Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 163 CHAPTER 9 I/O PORT port. • As with input port, when a pin jointly used for LCD is used as another peripheral function input,configure it as an input port. • When a PDR register is read, the value of the pin can be read, regardless of whether the peripheral function uses an input pin.
Page 164: Port E
CHAPTER 9 I/O PORT 9.11 Port E Port E is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions. Port E Configuration Port E is made up of the following elements. •...
Page 165 CHAPTER 9 I/O PORT Block Diagram of Port E Figure 9.11-1 Block Diagram of Port E LCD output Peripheral function input LCD enable Peripheral function input enable Hysteresis PDR read Automotive PDR write At bit operation instruction DDR read DDR write Stop, watch (SPL=1) ILSR3 read ILSR3...
Page 166: Port E Registers
CHAPTER 9 I/O PORT 9.11.1 Port E Registers This section describes the port E registers. Port E Register Function Table 9.11-2 lists the port E register functions. Table 9.11-2 Port E Register Function Register Data Read Read read-modify-write Write name As output port, outputs Pin state is "L"...
Page 167: Operations Of Port E
CHAPTER 9 I/O PORT 9.11.2 Operations of Port E This section describes the operations of port E. Operations of Port E Operation as an output port • Setting the corresponding DDR bit to "1" sets a pin as an output port. •...
Page 168 CHAPTER 9 I/O PORT Behavior during LCDC segment output • Sets the DDR register bit corresponding to the LCDC segment output pin to "0". • Prohibit output in pins jointly used by other peripheral functions. • In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use. Operation of the input level selection register •...
Page 169: Chapter 10 Timebase Timer
CHAPTER 10 TIMEBASE TIMER This chapter describes the functions and operations of the timebase timer. 10.1 Overview of Timebase Timer 10.2 Configuration of Timebase Timer 10.3 Registers of the Timebase Timer 10.4 Interrupts of Timebase Timer 10.5 Explanation of Timebase Timer Operations and Setup Procedure Example 10.6 Precautions when Using Timebase Timer...
Page 170: Overview Of Timebase Timer
CHAPTER 10 TIMEBASE TIMER 10.1 Overview of Timebase Timer The timebase timer is a 22-bit free-run down-counting counter which is synchronized with the main clock divided by two. The timebase timer has an interval timer function which can repeatedly generate interrupt requests at regular intervals. Interval Timer Function The interval timer function repeatedly generates interrupt requests at regular intervals by using the main clock divided by two as the count clock.
Page 171 CHAPTER 10 TIMEBASE TIMER Function of Clock Supply The clock supply function of the timebase timer provides the timer output for generating the main clock oscillation stabilization wait time and supplies the operating clock to the watchdog timer and to the prescaler used by some peripheral functions.
Page 172: Configuration Of Timebase Timer
CHAPTER 10 TIMEBASE TIMER 10.2 Configuration of Timebase Timer The timebase timer consists of the following blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) Block Diagram of Timebase Timer Figure 10.2-1 Block Diagram of Timebase Timer Timebase timer counter To prescaler...
Page 173 CHAPTER 10 TIMEBASE TIMER Timebase timer counter 22-bit down-counter that uses the main clock divided by two as the count clock Counter clear circuit This circuit controls clearing of the timebase counter. Interval timer selector This circuit selects the one bit from four bits in the 22 bits that make up the timebase timer counter to use the interval timer.
Page 174 CHAPTER 10 TIMEBASE TIMER...
Page 175: Registers Of The Timebase Timer
CHAPTER 10 TIMEBASE TIMER 10.3 Registers of the Timebase Timer Figure 10.3-1 shows the register of the timebase timer. Register of the Timebase Timer Figure 10.3-1 Register of the Timebase Timer Timebase timer control register Address bit7 bit6 bit5 bit4 bit3 bit2 bit1...
Page 176: Timebase Timer Control Register (Tbtc)
CHAPTER 10 TIMEBASE TIMER 10.3.1 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) selects the interval time, clears the counter, controls interrupts and checks the status. Timebase Timer Control Register (TBTC) Figure 10.3-2 Timebase Timer Control Register (TBTC) Initial value Address bit7...
Page 177 CHAPTER 10 TIMEBASE TIMER Table 10.3-1 Functional Description of Each Bit of Timebase Timer Control Register (TBTC) Bit name Function Set to "1" when interval time selected by the timebase timer elapses. TBIF: • Interrupt request is outputted when this bit and the timebase timer interrupt request enable bit Timebase timer (TBIE) are set to "1".
Page 178: Interrupts Of Timebase Timer
CHAPTER 10 TIMEBASE TIMER 10.4 Interrupts of Timebase Timer An interrupt request is triggered when the interval time selected by the timebase timer elapses (interval timer function). Interrupt when Interval Function is in Operation When the timebase timer counter counts down using the internal count clock and the selected timebase timer counter underflows, the timebase timer interrupt request flag bit (TBTC:TBIF) is set to "1".
Page 179 CHAPTER 10 TIMEBASE TIMER Register and Vector Table for Interrupts of Timebase Timer Table 10.4-2 Register and Vector Table for Interrupts of Timebase Timer Interrupt level setup register Vector table address Interrupt Interrupt source request No. Register Setting bit Upper Lower FFD4 FFD5...
Page 180: Explanation Of Timebase Timer Operations And Setup Procedure Example
CHAPTER 10 TIMEBASE TIMER 10.5 Explanation of Timebase Timer Operations and Setup Procedure Example This section describes the operations of the interval timer function of the timebase timer. Operations of Timebase Timer The counter of the timebase timer is initialized to "3FFFFF" after a reset and starts counting while being synchronized with the main clock divided by two.
Page 181 CHAPTER 10 TIMEBASE TIMER The counter of the timebase timer is also cleared and stops the operation if a reset occurs while the main clock is still running after the main clock oscillation stabilization wait time has elapsed. The counter, however, continues to operate during a reset if a count is required for the oscillation stabilization wait time.
Page 182 CHAPTER 10 TIMEBASE TIMER Setup Procedure Example Initial Setting The timebase timer is set up in the following procedure: 1) Disable interrupts. (TBTC:TBIE = 0) 2) Set the interval time. (TBTC:TBC1, 0) 3) Enable interrupts. (TBTC:TBIE = 1) 4) Clear the counter. (TBTC:TCLR = 1) Processing interrupts 1) Clear the interrupt request flag.
Page 183: Precautions When Using Timebase Timer
CHAPTER 10 TIMEBASE TIMER 10.6 Precautions when Using Timebase Timer Care must be taken for the following points when using the timebase timer. Precautions when Using Timebase Timer When setting the timer by program The timer cannot be recovered from interrupt processing, when the timebase timer interrupt request flag bit (TBTC:TBIF) is set to "1"...
Page 184 CHAPTER 10 TIMEBASE TIMER...
Page 185: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. 11.1 Overview of Watchdog Timer 11.2 Configuration of Watchdog Timer 11.3 Registers of the Watchdog Timer 11.4 Explanation of Watchdog Timer Operations and Setup Procedure Example 11.5 Precautions when Using Watchdog Timer...
Page 186: Overview Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Overview of Watchdog Timer The watchdog timer serves as a counter used to prevent programs from running out of control. Watchdog Timer Function The watchdog timer functions as a counter used to prevent programs from running out of control. Once the watchdog timer is activated, its counter needs to be cleared at specified intervals regularly.
Page 187: Configuration Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter • Reset control circuit • Watchdog timer clear selector • Counter clear control circuit • Watchdog timer control register (WDTC) Block Diagram of Watchdog Timer Figure 11.2-1 Block Diagram of Watchdog Timer Watchdog timer control register (WDTC)
Page 188 CHAPTER 11 WATCHDOG TIMER Count clock selector This selector selects the count clock of the watchdog timer counter. Watchdog timer counter This is a 1-bit counter that uses the output of either the timebase timer or watch prescaler as the count clock.
Page 189: Registers Of The Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.3 Registers of the Watchdog Timer Figure 11.3-1 shows the register of the watchdog timer. Register of The Watchdog Timer Figure 11.3-1 Register of The Watchdog Timer Watchdog timer control register (WDTC) Address bit7 bit6 bit5 bit4 bit3 bit2...
Page 190: Watchdog Timer Control Register (Wdtc)
CHAPTER 11 WATCHDOG TIMER 11.3.1 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates or clears the watchdog timer. Watchdog Timer Control Register (WDTC) Figure 11.3-2 Watchdog Timer Control Register (WDTC) Address Initial value bit7 bit6 bit5 bit4 bit3 bit2...
Page 191 CHAPTER 11 WATCHDOG TIMER Table 11.3-1 Functional Description of Each Bit of Watchdog Timer Control Register (WDTC) Bit name Function These bits select the count clock of the watchdog timer. Count clock switch bits Output cycle of timebase timer ( Output cycle of timebase timer ( Output cycle of watch prescaler ( CS1, CS0:...
Page 192: Explanation Of Watchdog Timer Operations And Setup Procedure Example
CHAPTER 11 WATCHDOG TIMER 11.4 Explanation of Watchdog Timer Operations and Setup Procedure Example The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. Operations of Watchdog Timer How to activate the watchdog timer • The timer of the watchdog timer is activated when "0101 "...
Page 193 CHAPTER 11 WATCHDOG TIMER Interval time The interval time varies depending on the timing for clearing the watchdog timer. Figure 11.4-1 shows the correlation between the clearing timing of the watchdog timer and the interval time when the timebase timer output 2 : main clock) is selected as the count clock (main clock = 4MHz).
Page 194: Precautions When Using Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.5 Precautions when Using Watchdog Timer Care must be taken for the following points when using the watchdog timer. Precautions when Using Watchdog Timer Stopping the watchdog timer Once activated, the watchdog timer cannot be stopped until a reset is generated. Selecting the count clock The count clock switch bits (WDTC:CS1,0) can be rewritten only when the watchdog control bits (WDTC:WTE3 to WTE0) are set to "0101...
Page 195: Chapter 12 Hardware Watchdog Timer
CHAPTER 12 HARDWARE WATCHDOG TIMER This chapter describes the functions and operations of the hardware watchdog timer. 12.1 Overview of Hardware Watchdog Timer 12.2 Configuration of Hardware Watchdog Timer 12.3 Registers of the Hardware Watchdog Timer 12.4 Explanation of Hardware Watchdog Timer Operations and Setup Procedure Example 12.5 Precautions when Using Hardware Watchdog Timer...
Page 196: Overview Of Hardware Watchdog Timer
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.1 Overview of Hardware Watchdog Timer The hardware watchdog timer serves as a counter used to prevent programs from running out of control. Hardware Watchdog Timer Function The hardware watchdog timer functions as a counter used to prevent programs from running out of control. Once the hardware watchdog timer is activated, its counter needs to be cleared at specified intervals regularly.
Page 197: Configuration Of Hardware Watchdog Timer
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.2 Configuration of Hardware Watchdog Timer The hardware watchdog timer consists of the following blocks: • Hardware watchdog timer counter • Reset control circuit • Hardware watchdog timer clear selector • Counter clear control circuit •...
Page 198 CHAPTER 12 HARDWARE WATCHDOG TIMER RC oscillator prescalar The RC oscillator prescaler divides the RC oscillator frequency by 2 times. Hardware watchdog timer counter This is a 1-bit counter that uses the output of RC oscillator prescalar as the count clock. Reset control circuit This circuit generates a reset signal when the hardware watchdog timer counter overflows.
Page 199: Registers Of The Hardware Watchdog Timer
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.3 Registers of the Hardware Watchdog Timer Figure 12.3-1 shows the register of the hardware watchdog timer. Register of The Hardware Watchdog Timer Figure 12.3-1 Register of The Hardware Watchdog Timer Hardware Watchdog timer control register (HWDC) Address bit7 bit6...
Page 200: Hardware Watchdog Timer Control Register (Hwdc)
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.3.1 Hardware Watchdog Timer Control Register (HWDC) The hardware watchdog timer control register (HWDC) activates or clears the hardware watchdog timer. Hardware Watchdog Timer Control Register (HWDC) Figure 12.3-2 Hardware Watchdog Timer Control Register (HWDC) Address Initial value bit7...
Page 201 CHAPTER 12 HARDWARE WATCHDOG TIMER Table 12.3-1 Functional Description of Each Bit of Hardware Watchdog Timer Control Register (HWDC) Bit name Function These bits are not used. bit7 Unused bits • The read value is "00". bit6 • Write has no effect on operation. These bits are reserved.
Page 202: Explanation Of Hardware Watchdog Timer Operations And Setup Procedure Example
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.4 Explanation of Hardware Watchdog Timer Operations and Setup Procedure Example The hardware watchdog timer generates a hardware watchdog reset when the hardware watchdog timer counter overflows. Operations of Hardware Watchdog Timer How to activate the hardware watchdog timer •...
Page 203 CHAPTER 12 HARDWARE WATCHDOG TIMER Interval time The interval time varies depending on the timing for clearing the hardware watchdog timer. Figure 12.4-1 shows the correlation between the clearing timing of the hardware watchdog timer and the interval time. Figure 12.4-1 Clearing Timing and Interval Time of hardware watchdog Timer Minimum time 327ms (MAX)/655ms(TYP) RC oscillator...
Page 204: Precautions When Using Hardware Watchdog Timer
CHAPTER 12 HARDWARE WATCHDOG TIMER 12.5 Precautions when Using Hardware Watchdog Timer Care must be taken for the following points when using the hardware watchdog timer. Precautions when Using Hardware Watchdog Timer Stopping the hardware watchdog timer Hareware watchdog is activated after reset. Once activated, the hardware watchdog timer cannot be stopped until a reset is generated.
Page 205: Chapter 13 Watch Prescaler
CHAPTER 13 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler. 13.1 Overview of Watch Prescaler 13.2 Configuration of Watch Prescaler 13.3 Registers of the Watch Prescaler 13.4 Interrupts of Watch Prescaler 13.5 Explanation of Watch Prescaler Operations and Setup Procedure Example 13.6 Precautions when Using Watch Prescaler 13.7 Sample Programs for Watch Prescaler...
Page 206: Overview Of Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.1 Overview of Watch Prescaler The watch prescaler is a 15-bit down-counting, free-run counter, which is synchronized with the subclock divided by two. It has an interval timer function that continuously generates interrupt requests at regular intervals. Interval Timer Function The interval timer function continuously generates interrupt requests at regular intervals, using the subclock divided by two as its count clock.
Page 207: Configuration Of Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.2 Configuration of Watch Prescaler The watch prescaler consists of the following blocks: • Watch prescaler counter • Counter clear circuit • Interval timer selector • Watch prescaler control register (WPCR) Block Diagram of Watch Prescaler Figure 13.2-1 Block Diagram of Watch Prescaler To oscillation stabilization wait timer of subclosk, watchdog timer, watch counter...
Page 208 CHAPTER 13 WATCH PRESCALER Watch prescaler counter (counter) This is a 15-bit down-counter that uses the subclock divided by two as its count clock. Counter clear circuit This circuit controls the clearing of the watch prescaler. Interval timer selector This circuit selects one out of the four bits used for the interval timer among 15 bits available in the watch prescaler counter.
Page 209: Registers Of The Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.3 Registers of the Watch Prescaler Figure 13.3-1 shows the register of the watch prescaler. Register of the Watch Prescaler Figure 13.3-1 Register of the Watch Prescaler Watch Prescaler Control Register (WDTC) Address bit7 bit6 bit5 bit4 bit3 bit2...
Page 210: Watch Prescaler Control Register (Wpcr)
CHAPTER 13 WATCH PRESCALER 13.3.1 Watch Prescaler Control Register (WPCR) The watch prescaler control register (WPCR) is a register used to select the interval time, clear the counter, control interrupts and check the status. Watch Prescaler Control Register (WPCR) Figure 13.3-2 Watch Prescaler Control Register (WPCR) Address bit7 Initial value...
Page 211 CHAPTER 13 WATCH PRESCALER Table 13.3-1 Functional Description of Each Bit of Watch Prescaler Control Register (WPCR) Bit name Function This bit becomes "1" when the selected interval time of the watch prescaler has elapsed. • Interrupt requests are generated when this bit and the interrupt request enable bit (WTIE) are set to WTIF: "1".
Page 212: Interrupts Of Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.4 Interrupts of Watch Prescaler An interrupt request is generated when the selected interval time of the watch prescaler has elapsed (interval timer function). Interrupts in Operation of Interval Timer Function (Watch Interrupts) In any mode other than the main stop mode, the watch interrupt request flag bit is set to "1" (WPCR:WTIF = 1), when the watch prescaler counter counts up by using the source oscillation of the subclock and the time of the interval timer has elapsed.
Page 213 CHAPTER 13 WATCH PRESCALER Note: If the interval time set for the watch prescaler is shorter than the oscillation stabilization wait time of the subclock, an interrupt request of the watch prescaler is generated during the oscillation stabilization wait time of the subclock required for recovery by an external interrupt upon the transition from the subclock mode or the sub PLL clock mode to the stop mode.
Page 214: Explanation Of Watch Prescaler Operations And Setup Procedure Example
CHAPTER 13 WATCH PRESCALER 13.5 Explanation of Watch Prescaler Operations and Setup Procedure Example The watch prescaler operates as an interval timer. Operations of Interval Timer Function (Watch Prescaler) The counter of the watch prescaler continues to count down using the subclock divided by two as its count clock as long as the subclock oscillates.
Page 215 CHAPTER 13 WATCH PRESCALER Figure 13.5-1 Operating Examples of Watch Prescaler Counter value (count down) 7FFF Count value detected in WATR:SWT3, 2, 1, 0 Count value detected in WPCR:WTC1, 0 Interval cycle (WPCR:WTC1, 0 = 11B) 0000 Subclock oscillation Subclock oscillation Clear by transferring 4) Counter clear stabilization wait time...
Page 216: Precautions When Using Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.6 Precautions when Using Watch Prescaler Shown below are the precautions that must be followed when using the watch prescaler. The watch prescaler cannot be used in single system clock option product. Precautions when Using Watch Prescaler When setting the prescaler by program The prescaler cannot be recovered from interrupt processing when the watch interrupt request flag bit (WPCR:WTIF) is set to "1"...
Page 217: Sample Programs For Watch Prescaler
CHAPTER 13 WATCH PRESCALER 13.7 Sample Programs for Watch Prescaler We provide sample programs that can be used to operate the watch prescaler. Sample Programs for Watch Prescaler For information about sample programs for the watch prescaler, refer to " Sample programs"...
Page 218 CHAPTER 13 WATCH PRESCALER...
Page 219: Chapter 14 Watch Counter
CHAPTER 14 WATCH COUNTER This chapter describes the functions and operations of the watch counter. 14.1 Overview of Watch Counter 14.2 Configuration of Watch Counter 14.3 Registers of Watch Counter 14.4 Interrupts of Watch Counter 14.5 Explanation of Watch Counter Operations and Setup Procedure Example 14.6 Precautions when Using Watch Counter 14.7 Sample Programs for Watch Counter...
Page 220: Overview Of Watch Counter
CHAPTER 14 WATCH COUNTER 14.1 Overview of Watch Counter The watch counter can generate interrupt requests ranging from min. 125ms to max. 63s intervals. Watch Counter The watch counter performs counting for the number of times specified in the register by using the selected count clock and generates an interrupt request.
Page 221: Configuration Of Watch Counter
CHAPTER 14 WATCH COUNTER 14.2 Configuration of Watch Counter Figure 14.2-1 shows the block diagram of the watch counter. Block Diagram of Watch Counter Figure 14.2-1 Block Diagram of Watch Counter Watch counter control register (WCSR) ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 Interrupt of...
Page 222 CHAPTER 14 WATCH COUNTER Counter This is a 6-bit down-counter that uses the output clock of the watch prescaler as its count clock. Watch counter control register (WCSR) This register controls interrupts and checks the status. Watch counter data register (WCDR) This register sets the interval time and selects the count clock.
Page 223: Registers Of Watch Counter
CHAPTER 14 WATCH COUNTER 14.3 Registers of Watch Counter Figure 14.3-1 shows the registers of the watch counter. Registers of Watch Counter Figure 14.3-1 Registers Related to Watch Counter Watch counter data register (WCDR) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...
Page 224: Watch Counter Data Register (Wcdr)
CHAPTER 14 WATCH COUNTER 14.3.1 Watch Counter Data Register (WCDR) The watch counter data register (WCDR) is used to select the count clock and set the counter reload value. Watch Counter Data Register (WCDR) Figure 14.3-2 Watch Counter Data Register (WCDR) bit7 bit6 bit5 bit4...
Page 225: Chapter 14 Watch Counter
CHAPTER 14 WATCH COUNTER Table 14.3-1 Functional Description of Each Bit of Watch Counter Data Register (WCDR) Bit name Function These bits select the clock for the watch counter. bit7 CS1, 0: "00" = 2 , "01" = 2 , "10" = 2 , "11"...
Page 226: Watch Counter Control Register (Wcsr)
CHAPTER 14 WATCH COUNTER 14.3.2 Watch Counter Control Register (WCSR) The watch counter control register (WCSR) is used to control the operation and interrupts of the watch counter. It can also read the count value. Watch Counter Control Register (WCSR) Figure 14.3-3 Watch Counter Control Register (WCSR) bit7 bit6...
Page 227 CHAPTER 14 WATCH COUNTER Table 14.3-2 Functional Description of Each Bit of Watch Counter Status Register (WCSR) Bit name Function • This bit activates the watch counter and selects whether to enable interrupts of the watch counter or those of the watch prescaler. When set to "0":The watch counter is cleared and stopped.
Page 228: Interrupts Of Watch Counter
CHAPTER 14 WATCH COUNTER 14.4 Interrupts of Watch Counter The watch counter outputs interrupt requests when the counter underflows (counter value = "000001 "). Interrupts of Watch Counter When the counter of the watch counter underflows, the interrupt request flag bit (WCFLG) of the watch counter control register (WCSR) is set to "1".
Page 229: Explanation Of Watch Counter Operations And Setup Procedure Example
CHAPTER 14 WATCH COUNTER 14.5 Explanation of Watch Counter Operations and Setup Procedure Example The watch counter counts down for the number of times specified in the count value by RCTR5 to RCTR0 bits, using the count clock selected by CS1 and CS0 bits, when the ISEL bit is set to "1".
Page 230 CHAPTER 14 WATCH COUNTER Note: When the operation is reactivated by WCSR:ISEL=0 after counter stop, please reactivate after confirming reading WCSR:CTR[5:0] twice, and clearing to CTR[5:0]=000000 Operation in Sub Stop Mode When the device enters the sub stop mode, the watch counter stops the count operation and the watch prescaler is also cleared.
Page 231: Precautions When Using Watch Counter
CHAPTER 14 WATCH COUNTER 14.6 Precautions when Using Watch Counter Shown below are the precautions that must be followed when using the watch counter. • If the watch prescaler is cleared during the operation of the watch counter, the watch counter may not be able to perform normal operation.
Page 232: Sample Programs For Watch Counter
CHAPTER 14 WATCH COUNTER 14.7 Sample Programs for Watch Counter We provide sample programs that can be used to operate the watch counter. Sample Programs for Watch Counter For information about sample programs for the watch counter, refer to " Sample Programs"...
Page 233: Chapter 15 Wild Register
CHAPTER 15 WILD REGISTER This chapter describes the functions and operations of the wild register. 15.1 Overview of Wild Register 15.2 Configuration of Wild Register 15.3 Registers of Wild Register 15.4 Operating Description of Wild Register 15.5 Typical Hardware Connection Example...
Page 234: Overview Of Wild Register
CHAPTER 15 WILD REGISTER 15.1 Overview of Wild Register The wild register function can be used to patch the program which has the bugs by specifying the addresses and substitute data in internal registers. The primary purpose of this register is to substitute ROM code in the ROM space. The wild register consists of 3-byte data setting registers, 3-byte upper address setting registers, 3-byte lower address setting registers, a 1-byte address compare enable register, and a 1-byte data test register.
Page 235: Configuration Of Wild Register
CHAPTER 15 WILD REGISTER 15.2 Configuration of Wild Register The block diagram of the wild register is shown below. The wild register consists of the following blocks: • Memory area block Wild register data setup register (WRDR0 to WRDR2) Wild register address setup register (WRAR0 to WRAR2) Wild register address compare enable register (WREN) Wild register data test setup register (WROR) •...
Page 236 CHAPTER 15 WILD REGISTER Memory area block The memory area block consists of the wild register data setup registers (WRDR), wild register address setup registers (WRAR), wild register address compare enable register (WREN) and wild register data test setup register (WROR). The wild register function is used to specify the addresses and data that need to be replaced.
Page 237: Registers Of Wild Register
CHAPTER 15 WILD REGISTER 15.3 Registers of Wild Register The registers of the wild register include the wild register data setup registers (WRDR), wild register address setup registers (WRAR), wild register address compare enable register (WREN) and wild register data test setup register (WROR). Registers Related to Wild Register Figure 15.3-1 Registers Related to Wild Register Wild register data setup registers (WRDR0 to WRDR2)
Page 238 CHAPTER 15 WILD REGISTER Wild Register Number Each wild register address setup register (WRAR) and wild register data setup register (WRDR) has its corresponding wild register number. Table 15.3-1 Wild Register Numbers Corresponding to Wild Register Address Setup Registers and Wild Register Data Setup Registers Wild register number Wild register address setup register (WRAR)
Page 239: Wild Register Data Setup Registers (Wrdr0 To Wrdr2)
CHAPTER 15 WILD REGISTER 15.3.1 Wild Register Data Setup Registers (WRDR0 to WRDR2) The wild register data setup registers (WRDR0 to WRDR2) use the wild register function to specify the data to be amended. Wild Register Data Setup Registers (WRDR0 to WRDR2) Figure 15.3-2 Wild Register Data Setup Registers (WRDR0 to WRDR2) WRDR0 Address...
Page 240: Wild Register Address Setup Registers (Wrar0 To Wrar2)
CHAPTER 15 WILD REGISTER 15.3.2 Wild Register Address Setup Registers (WRAR0 to WRAR2) The wild register address setup registers (WRAR0 to WRAR2) set the address to be amended by the wild register function. Wild Register Address Setup Registers (WRAR0 to WRAR2) Figure 15.3-3 Wild Register Address Setup Registers (WRAR0 to WRAR2) WRAR0 Address...
Page 241: Wild Register Address Compare Enable Register (Wren)
CHAPTER 15 WILD REGISTER 15.3.3 Wild Register Address Compare Enable Register (WREN) The wild register address compare enable register (WREN) enables/disables the operation of the wild register in accordance with each wild register number. Wild Register Address Compare Enable Register (WREN) Figure 15.3-4 Wild Register Address Compare Enable Register (WREN) Address bit7...
Page 242: Wild Register Data Test Setup Register (Wror)
CHAPTER 15 WILD REGISTER 15.3.4 Wild Register Data Test Setup Register (WROR) The wild register data test setup register (WROR) enables/disables reading from the corresponding wild register data setup register (WRDR0 to WRDR2). Wild Register Data Test Setup Register (WROR) Figure 15.3-5 Wild Register Data Test Setup Register (WROR) Address bit7...
Page 243: Operating Description Of Wild Register
CHAPTER 15 WILD REGISTER 15.4 Operating Description of Wild Register This section describes the setup procedure for the wild register. Setup Procedure for Wild Register Prepare a special program that can read the value to be set in the wild register from external memory (e.g. PROM or FRAM) in the user program before executing the program.
Page 244: Typical Hardware Connection Example
CHAPTER 15 WILD REGISTER 15.5 Typical Hardware Connection Example Shown below is a typical hardware connection example applied when using the wild register function. Hardware Connection Example Figure 15.5-1 Typical Hardware Connection Example PROM (Stores correction program) MB95170J series...
Page 245: Chapter 16 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER This chapter describes the functions and operations of the 8/16-bit composite timer. 16.1 Overview of 8/16-bit Composite Timer 16.2 Configuration of 8/16-bit Composite Timer 16.3 Channels of 8/16-bit Composite Timer 16.4 Pins of 8/16-bit Composite Timer 16.5 Registers of 8/16-bit Composite Timer 16.6 Interrupts of 8/16-bit Composite Timer 16.7 Operating Description of Interval Timer Function (One-shot Mode)
Page 246: Overview Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.1 Overview of 8/16-bit Composite Timer The 8/16-bit composite timer consists of two 8-bit counters and can be used as two 8-bit timers, or one 16-bit timer if they are connected in cascade. The 8/16-bit composite timer has the following functions: •...
Page 247 CHAPTER 16 8/16-BIT COMPOSITE TIMER PWC Timer Function When the PWC timer function is selected, the width and cycle of an external input pulse can be measured. In this operation mode, the counter starts counting from "00 " upon detection of a count start edge of an external input signal and transfers the count value to a register to generate an interrupt upon detection of a count end edge.
Page 248: Configuration Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.2 Configuration of 8/16-bit Composite Timer The 8/16-bit composite timer consists of the following blocks: • 8-bit counter x 2 channels • 8-bit comparator (including a temporary latch) x 2 channels • 8/16-bit composite timer 00/01 data register x 2 channels (T00DR/T01DR) •...
Page 249 CHAPTER 16 8/16-BIT COMPOSITE TIMER Block Diagram of 8/16-bit Composite Timer Figure 16.2-1 Block Diagram of 8/16-bit Composite Timer T00CR0 IFE C2 C1 C0 F3 F2 F1 F0 Timer 00 CK00 8-bit counter Clocks from prescaler/TBT Count Timer output clock CK06 TO00 selector...
Page 250 CHAPTER 16 8/16-BIT COMPOSITE TIMER 8/16-bit composite timer 00/01 control status registers 0 (T00CR0/T01CR0) These registers are used to select the timer operation mode, select the count clock, and to enable or disable IF flag interrupts. 8/16-bit composite timer 00/01 control status registers 1 (T00CR1/T01CR1) These registers are used to control interrupt flags, timer output, and timer operation.
Page 251: Channels Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.3 Channels of 8/16-bit Composite Timer This section describes the channels of 8/16-bit composite timer. Channels of 8/16-bit Composite Timer This series contains two channels of 8/16-bit composite timer. In one channel, there are two 8-bit counters. Each counter can be used as two 8-bit timers or one 16-bit timer.
Page 252: Pins Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.4 Pins of 8/16-bit Composite Timer This section describes the pins related to the 8/16-bit composite timer. Pins Related to 8/16-bit Composite Timer The external pins related to the 8/16-bit composite timer are TO00, TO01, EC0, and EC1. TII0 is for internal chip connection.
Page 253: Registers Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.5 Registers of 8/16-bit Composite Timer This section describes the registers related to the 8/16-bit composite timer. Registers Related to 8/16-bit Composite Timer Figure 16.5-1 Registers Related to 8/16-bit Composite Timer 8/16-bit composite timer 00/01 control status register 0 (T00CR0/T01CR0) Address bit7 bit6...
Page 254: 8/16-Bit Composite Timer 00/01 Control Status Register 0 (T00Cr0/T01Cr0)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.5.1 8/16-bit Composite Timer 00/01 Control Status Register 0 (T00CR0/T01CR0) The 8/16-bit composite timer 00/01 control status register 0 (T00CR0/T01CR0) selects the timer operation mode, selects the count clock, and enables or disables IF flag interrupts. The T00CR0 and T01CR0 registers correspond to timers 00 and 01, respectively.
Page 255 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-1 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register 0 (T00CR0/T01CR0) (1 / 2) Bit name Function • This bit enables or disables IF flag interrupts. IFE: Setting this bit to "0" : disables IF flag interrupts. bit7 IF flag interrupt enable Setting this bit to "1"...
Page 256 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-1 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register 0 (T00CR0/T01CR0) (2 / 2) Bit name Function These bits select the timer operation mode. • The PWM timer function (variable-cycle mode; F3, F2, F1, F0 = "0100 ") is set by either the T00CR0 (timer 00) register or T01CR0 (timer 01) register.
Page 257 CHAPTER 16 8/16-BIT COMPOSITE TIMER...
Page 258: 8/16-Bit Composite Timer 00/01 Control Status Register 1 (T00Cr1/T01Cr1)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.5.2 8/16-bit Composite Timer 00/01 Control Status Register 1 (T00CR1/T01CR1) 8/16-bit composite timer 00/01 control status register 1 (T00CR1/T01CR1) controls the interrupt flag, timer output, and timer operations. T00CR1 and T01CR1 registers correspond to timers 00 and 01, respectively. 8/16-bit Composite Timer 00/01 Control Status Register 1 (T00CR1/T01CR1) Figure 16.5-3 8/16-bit Composite Timer 00/01 Control Status Register 1 (T00CR1/T01CR1) bit7...
Page 259 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-2 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register 1 (1 / 2) Bit name Function This bit enables or stops timer operation. Writing "1" : allows timer operation to start from count value "00 ".
Page 260 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-2 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register 1 (2 / 2) Bit name Function • This bit is set to "1" when a count value is stored in the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) upon completion of pulse width measurement in PWC timer function.
Page 261 CHAPTER 16 8/16-BIT COMPOSITE TIMER...
Page 262: 8/16-Bit Composite Timer 00/01 Timer Mode Control Register (Tmcr0)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.5.3 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0) The 8/16-bit composite timer 00/01 timer mode control register (TMCR0) selects the filter function, 8-bit or 16-bit operation mode, and signal input to timer 00 and to indicate the timer output value.
Page 263 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-3 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0) (1 / 2) Bit name Function This bit indicates the output value of timer 01. When the timer starts operation (T00CR1/ T01CR1:STA = 1), the value in the bit changes depending on the selected timer function.
Page 264 CHAPTER 16 8/16-BIT COMPOSITE TIMER Table 16.5-3 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Timer Mode Control Register (TMCR0) (2 / 2) Bit name Function These bits select the filter function for the external signal (EC00) to timer 00 when the PWC timer or input capture function has been selected.
Page 265: 8/16-Bit Composite Timer 00/01 Data Register (T00Dr/T01Dr)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.5.4 8/16-bit Composite Timer 00/01 Data Register (T00DR/T01DR) The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is used to write the maximum value counted during interval timer or PWM timer operation and to read the count value during PWC timer or input capture operation.
Page 266 CHAPTER 16 8/16-BIT COMPOSITE TIMER PWM timer functions (variable-cycle) The 8/16-bit composite timer 00 data register (T00DR) and 8/16-bit composite timer 01 data register (T01DR) are used to set "L" pulse width timer and cycle, respectively. When the timer starts operation (T00CR1/T01CR1:STA = 1), the value of each register is transferred to the latch in the 8-bit comparator and two counters start counting from timer output "L".
Page 267 CHAPTER 16 8/16-BIT COMPOSITE TIMER Read and write operations Read and write operations of T00DR and T01DR are performed in the following manner during 16-bit operation and PWM timer function (variable-cycle). • Read from T01DR: Read access from the register also involves storing the T00DR value into the internal read buffer.
Page 268: Interrupts Of 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.6 Interrupts of 8/16-bit Composite Timer The 8/16-bit composite timer generates the following types of interrupts to each of which an interrupt number and interrupt vector are assigned. • Timer 00 interrupt • Timer 01 interrupt Timer 00 Interrupt Table 16.6-1 explains the timer 00 interrupt and its source.
Page 269 CHAPTER 16 8/16-BIT COMPOSITE TIMER Registers and Vector Tables Related to Interrupts of 8/16-bit Composite Timer Table 16.6-3 Registers and Vector Tables Related to Interrupts of 8/16-bit Composite Timer Interrupt level setup register Vector table address Interrupt Interrupt source request No. Register Setting bit Upper...
Page 270: Operating Description Of Interval Timer Function (One-Shot Mode)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.7 Operating Description of Interval Timer Function (One- shot Mode) This section describes the operations of the interval timer function (one-shot mode) for the 8/16-bit composite timer. Operation of Interval Timer Function (One-shot Mode) The composite timer requires the register settings shown in Figure 16.7-1 to serve as the interval timer function.
Page 271 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.7-2 Operation of Interval Timer Function in 8-bit Mode (Timer 0) Counter value FF Time Timer cycle T00/01DR value modified (FF T00/01DR Cleared value (FF by program IF bit STA bit Reactivated Reactivated Automatically cleared Automatically cleared Inverted Reactivated with output initial value unchanged ("0")
Page 272: Operating Description Of Interval Timer Function (Continuous Mode)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.8 Operating Description of Interval Timer Function (Continuous Mode) This section describes the interval timer function (continuous mode operation) of the 8/16-bit composite timer. Operation of Interval Timer Function (Continuous Mode) The composite timer requires the register settings shown in Figure 16.8-1 to serve as the interval timer function (continuous mode).
Page 273 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.8-2 Operating Diagram of Interval Timer Function (Continuous Mode) Compare value Compare value Compare value Compare value Time T00/01DR value modified (FF T00/01DR value (E0 Cleared by program IF bit STA bit Activated Matched Matched Matched Matched...
Page 274: Operating Description Of Interval Timer Function (Free-Run Mode)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.9 Operating Description of Interval Timer Function (Free-run Mode) This section describes the operation of the interval timer function (free-run mode) for the 8/16-bit composite timer. Operation of Interval Timer Function (Free-run Mode) The composite timer requires the settings shown in Figure 16.9-1 to serve as the interval timer function (free-run mode).
Page 275 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.9-2 Operating Diagram of Interval Timer Function (Free-run Mode) Counter value Time Although the T00/01DR value is modified, it is not updated into the comparison latch. T00/01DR value (E0 Cleared by program IF bit STA bit Activated Matched...
Page 276: Operating Description Of Pwm Timer Function (Fixed-Cycle Mode)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.10 Operating Description of PWM Timer Function (Fixed-cycle mode) This section describes the operation of the PWM timer function (fixed-cycle mode) for the 8/16-bit composite timer. Operation of PWM Timer Function (Fixed-cycle Mode) The composite timer requires the settings shown in Figure 16.10-1 to serve as the PWM timer function (fixed-cycle mode).
Page 277 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.10-2 Operating Diagram of PWM Timer Function (Fixed-cycle Mode) T00/01DR register value: "00 " (duty ratio = 0%) Counter value FFH00H PWM waveform T00/01DR register value: "80 " (duty ratio = 50%) Counter value FFH00H PWM waveform T00/01DR register value: "FF...
Page 278: Operating Description Of Pwm Timer Function (Variable-Cycle Mode)
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.11 Operating Description of PWM Timer Function (Variable- cycle Mode) This section describes the operations of the PWM timer function (variable-cycle mode) for the 8/16-bit composite timer. Operation of PWM Timer Function (Variable-cycle Mode) The composite timer requires the settings shown in Figure 16.11-1 to serve as the PWM timer function (variable-cycle mode).
Page 279 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.11-2 Operating Diagram of PWM Timer Function (Variable-cycle Mode) T00DR register value: "80 H ", and T01DR register value: "80 H " (duty ratio = 0%) (timer 00 value >= timer 01 value) Counter timer 00 value 00 H 80 H 00 H 80 H 00 H...
Page 280: 16.12 Operating Description Of Pwc Timer Function
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.12 Operating Description of PWC Timer Function This section describes the operations of the PWC timer function for the 8/16-bit composite timer. Operation of PWC Timer Function The composite timer requires the settings shown in Figure 16.12-1 to serve as the PWC timer function. Figure 16.12-1 Settings for PWC Timer Function bit7 bit6...
Page 281 CHAPTER 16 8/16-BIT COMPOSITE TIMER Note also that an overflow toggles the timer output. The timer output initial value can be set by the timer output initial value bit (T00CR1/T01CR1:SO). When the timer stops operation, the timer output bit (TMCR0:TO1/TO0) holds the last value. The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) must be nullified if an interrupt occurs before the timer is activated (before "1"...
Page 282: 16.13 Operating Description Of Input Capture Function
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.13 Operating Description of Input Capture Function This section describes the operations of the input capture function for the 8/16-bit composite timer. Operation of Input Capture Function The composite timer requires the settings shown in Figure 16.13-1 to serve as the input capture function. Figure 16.13-1 Settings for Input Capture Function bit7 bit6...
Page 283 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.13-2 Operating Diagram of Input Capture Function Capture value in T00/01DR Rising edge of capture Falling edge of capture Rising edge of Falling edge of capture capture External input Counter free-run mode Counter clear mode...
Page 284: 16.14 Operating Description Of Noise Filter
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.14 Operating Description of Noise Filter This section describes the operations of the noise filter for the 8/16-bit composite timer. When the input capture or PWC timer function has been selected, a noise filter can be used to eliminate the pulse noise of the signal from the external input pin (EC00/EC01).
Page 285: 16.15 States In Each Mode During Operation
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.15 States in Each Mode during Operation This section describes how the 8/16-bit composite timer behaves when the microcontroller enters watch mode or stop mode or when a suspend (T00CR1/ T01CR1:HO = "1") request is issued during operation. When Interval Timer, Input Capture, or PWC Function Has Been Selected Figure 16.15-1 shows how the counter value changes when transition to watch mode or stop mode or a suspend request occurs during operation of the 8/16-bit composite timer.
Page 286 CHAPTER 16 8/16-BIT COMPOSITE TIMER Figure 16.15-2 Operations of Counter in Standby Mode or in Pause (Serving as PWM Timer) Counter value Time Delay of oscillation stabilization wait time T00/01DR value (FF STA bit PWM timer output pin Sleep mode Maintains the level prior to stop Maintains the level prior to hold SLP bit...
Page 287: 16.16 Precautions When Using 8/16-Bit Composite Timer
CHAPTER 16 8/16-BIT COMPOSITE TIMER 16.16 Precautions when Using 8/16-bit Composite Timer This section explains the precautions to be taken when using the 8/16-bit composite timer. Precautions when Using 8/16-bit Composite Timer When changing the timer function by using the timer operation mode select bits (T00CR0/T01CR0:F3, F2, F1, F0), the timer operation must be stopped (T00CR1/T01CR1:STA = 0) before clearing the interrupt flag (T00CR1/T01CR1:IF, IR), interrupt enable bits (T00CR1/T01CR1:IE, T00CR0/T01CR0:IFE) and buffer full flag (T00CR1/T01CR1:BF).
Page 288 CHAPTER 16 8/16-BIT COMPOSITE TIMER...
Page 289: Chapter 17 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER This chapter describes the functions and operations of the 16-bit PPG timer. 17.1 Overview of 16-bit PPG Timer 17.2 Configuration of 16-bit PPG Timer 17.3 Channels of 16-bit PPG Timer 17.4 Pins of 16-bit PPG Timer 17.5 Registers of 16-bit PPG Timer 17.6 Interrupts of 16-bit PPG Timer 17.7 Explanation of 16-bit PPG Timer Operations and Setup Procedure...
Page 290: Overview Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.1 Overview of 16-bit PPG Timer The 16-bit PPG timer can generate a PWM (Pulse Width Modulation) output or one-shot (square wave) output, and the period and duty of the output waveform can be changed by software freely.
Page 291: Configuration Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.2 Configuration of 16-bit PPG Timer Shown below is the block diagram of the 16-bit PPG timer. Block Diagram of 16-bit PPG Timer Figure 17.2-1 Block Diagram of 16-bit PPG Timer When upper 8 bits of duty setting register are written but lower 8 bits are not 16-bit PPG cycle...
Page 292: Channels Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.3 Channels of 16-bit PPG Timer This section describes the channels of the 16-bit PPG timer. Channels of 16-bit PPG Timer This series has eight 16-bit PPG timers. Table 17.3-1 and 17.3-2 show the correspondence among the channel, pin and register. Table 17.3-1 Pins of 16-bit PPG Timer Channel Pin name...
Page 293: Pins Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.4 Pins of 16-bit PPG Timer This section describes the pins of the 16-bit PPG timer. Pins of 16-bit PPG Timer The following sections describe only the 16-bit PPG timer in ch.0. The other channels are the same as it. The pins related to the 16-bit PPG timer are namely the PPG0 pin.
Page 294 CHAPTER 17 16-BIT PPG TIMER Block Diagrams of Pins Related to 16-bit PPG Figure 17.4-1 Block Diagram of Pin Related to 16-bit PPG (PPG0, PPG1) Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up PDR read Automotive...
Page 295 CHAPTER 17 16-BIT PPG TIMER Figure 17.4-3 Block Diagram of Pin Related to 16-bit PPG (PPG6, PPG7) Peripheral function input Peripheral function output enable Peripheral function output Hysteresis Pull-up Automotive PDR read Selectalbe only P94 and P95 PDR write In bit operation instruction DDR read DDR write Stop, Watch (SPL=1)
Page 296: Registers Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.5 Registers of 16-bit PPG Timer This section describes the registers of the 16-bit PPG timer. Registers of 16-bit PPG Timer Figure 17.5-1 Registers of 16-bit PPG Timer 16-bit PPG down counter register (upper): PDCRH Address bit7 bit6...
Page 297 CHAPTER 17 16-BIT PPG TIMER (Continued) 16-bit PPG duty setting buffer register (upper): PDUTH Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 0FAE PDUTH0 DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08 11111111 0FB4 PDUTH1 0FBA PDUTH2 0FA8 PDUTH3 0F2E...
Page 298: 16- Bit Ppg Down Counter Registers (Pdcrh0, Pdcrl0)
CHAPTER 17 16-BIT PPG TIMER 17.5.1 16- bit PPG Down Counter Registers (PDCRH0, PDCRL0) The 16-bit PPG down counter registers (PDCRH0, PDCRL0) form a 16-bit register which is used to read the count value from the 16-bit PPG down-counter. 16-bit PPG Down Counter Registers (PDCRH0, PDCRL0) Figure 17.5-2 16-bit PPG Down Counter Registers (PDCRH0, PDCRL0) 16-bit PPG down counter register (upper) PDCRH0 Address...
Page 299: 16-Bit Ppg Cycle Setting Buffer Registers (Pcsrh0, Pcsrl0)
CHAPTER 17 16-BIT PPG TIMER 17.5.2 16-bit PPG Cycle Setting Buffer Registers (PCSRH0, PCSRL0) The 16-bit PPG cycle setting buffer registers are used to set the cycle for the output pulses generated by the PPG. 16-bit PPG Cycle Setting Buffer Registers (PCSRH0, PCSRL0) Figure 17.5-3 16-bit PPG Cycle Setting Buffer Registers (PCSRH0, PCSRL0) 16-bit PPG cycle setting buffer register (upper) PCSRH0 Address...
Page 300: 16-Bit Ppg Duty Setting Buffer Registers (Pduth0, Pdutl0)
CHAPTER 17 16-BIT PPG TIMER 17.5.3 16-bit PPG Duty Setting Buffer Registers (PDUTH0, PDUTL0) The 16-bit PPG duty setting buffer registers control the duty ratio for the output pulses generated by the PPG. 16-bit PPG Duty Setting Buffer Registers (PDUTH0, PDUTL0) Figure 17.5-4 16-bit PPG Duty Setting Buffer Registers (PDUTH0, PDUTL0) 16-bit PPG duty setting buffer register (upper) PDUTH0 Address...
Page 301 CHAPTER 17 16-BIT PPG TIMER...
Page 302: 16-Bit Ppg Status Control Register (Pcnth0, Pcntl0)
CHAPTER 17 16-BIT PPG TIMER 17.5.4 16-bit PPG Status Control Register (PCNTH0, PCNTL0) The 16-bit PPG status control register is used to enable and disable the 16-bit PPG timer and also to set the operating status for the software trigger, retrigger control interrupt, and output polarity.
Page 303 CHAPTER 17 16-BIT PPG TIMER Table 17.5-1 16-bit PPG Status Control Register, Upper Byte (PCNTH0) Bit name Function This bit is used to enable/stop PPG timer operation. When the bit is set to "0", the PPG operation halts immediately and the PPG output goes to the CNTE: bit7 initial level ("L"...
Page 304 CHAPTER 17 16-BIT PPG TIMER 16-bit PPG Status Control Register, Lower Byte (PCNTL0) Figure 17.5-6 16-bit PPG Status Control Register, Lower Byte (PCNTL0) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0042 PCNTH0 00000000 CNTE STRG MDSE RTRG CKS2 CKS1 CKS0 PGMS 0044...
Page 305 CHAPTER 17 16-BIT PPG TIMER Table 17.5-2 16-bit PPG Status Control Register, Lower Byte (PCNTL0) Bit name Function EGS1: This bit determines whether to allow or disallow the falling edge of TRG input to stop operation. bit7 Hardware trigger When the bit is set to "0", the falling edge of TRG has no effect on operation. enable bit1 When the bit is set to "1", the operation is stopped by the falling edge of TRG.
Page 306: Interrupts Of 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.6 Interrupts of 16-bit PPG Timer The 16-bit PPG timer can generate interrupt requests in the following cases: • When a trigger or counter borrow occurs • When a rising edge of PPG is generated in normal polarity •...
Page 307: Explanation Of 16-Bit Ppg Timer Operations And Setup Procedure Example
CHAPTER 17 16-BIT PPG TIMER 17.7 Explanation of 16-bit PPG Timer Operations and Setup Procedure Example The 16-bit PPG timer can operate in PWM mode or one-shot mode. In addition, a retrigger function can be used in the 16-bit PPG timer. PWM Mode (MDSE of PCNTH Register: bit 5 = 0) In PWM operation mode, the 16-bit PPG cycle setting buffer register (PCSRH0, PCSRL0) values are loaded and the 16-bit down-counter starts down-count operation when a software trigger is inputted or a...
Page 308 CHAPTER 17 16-BIT PPG TIMER Invalidating the retrigger (RTRG of PCNTH0 register: bit 4 = 0) Figure 17.7-1 When Retrigger Is Invalid in PWM Mode 16-bit down counter value Time Rising edge detected Trigger ignored Software trigger (Normal polarity) (Inverted polarity) T : Count clock cycle (1)=n ×...
Page 309 CHAPTER 17 16-BIT PPG TIMER One-shot Mode (MDSE of PCNTH0 Register: bit 5 = 1) One-shot operation mode can be used to output a single pulse with a specified width when a valid trigger input occurs. When retriggering is enabled and a valid trigger is detected during the counter operation, the down counter value is reloaded.
Page 310 CHAPTER 17 16-BIT PPG TIMER Hardware Trigger "Hardware trigger" refers to PPG activation by signal input to the TRG input pin. When EGS1 and EGS0 are set to "11" and the hardware trigger is used with TRG input, PPG starts operation on a rising edge and halts the operation upon the detection of a falling edge.
Page 311: Precautions When Using 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.8 Precautions when Using 16-bit PPG Timer Shown below are the precautions that must be followed when using the 16-bit PPG timer. Precautions when Using 16-bit PPG Timer Precautions when setting the program Do not use the retrigger if the same values are set for the cycle and duty. If used, the PPG output will go to the "L"...
Page 312: Sample Programs For 16-Bit Ppg Timer
CHAPTER 17 16-BIT PPG TIMER 17.9 Sample Programs for 16-bit PPG Timer We provide sample programs that can be used to operate the 16-bit PPG timer. Sample Programs for 16-bit PPG Timer For information about the sample programs for the 16-bit PPG timer, refer to " Sample Programs"...
Page 313 CHAPTER 17 16-BIT PPG TIMER How to start PPG operation by software The software trigger bit (PCNTH0 STGR) is used. What to be controlled Software trigger bit (STGR) When starting PPG operation by software Set the bit to "1" How to enable/disable the retrigger function of the software trigger The retrigger enable bit (PCNTH0 RTRG) is used.
Page 314 CHAPTER 17 16-BIT PPG TIMER How to set the PPG output to the "H" or "L" level The PPG output mask enable bit (PCNTH0 PGMS) and the output inversion bit (PCNTL0 OSEL) are used. PPG output mask enable bit Output inversion bit What to be controlled (PGMS) (OSEL)
Page 315 CHAPTER 17 16-BIT PPG TIMER How to enable/disable/clear interrupts Interrupt request enable flag, Interrupt request flag The interrupt request enable bit (PCNTL0 IREN) is used to enable interrupts. What to be controlled Interrupt request enable bit (IREN) When disabling interrupt request Set the bit to "0"...