Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET

Table 19.3-1 Functional Description of Low Voltage/CPU operating Detection Reset Control Register
Bit name
bit7/ Reserved:
bit6 Reserved bits
bit5/ Reserved:
bit4 Reserved bits
bit3 CL:
CPU operating
detection clear bit
bit2 LVRF:
Low voltage
detection flag bit
bit1 Reserved:
Reserved bit
bit0 CPUF:
CPU
Note: These bits should write "0".
Note: These bits should write "1".
This bit is a bit that clears the counter of CPU operating detection
circuit. When "0" is written in the CL bit, the counter of CPU
operating detection circuit is cleared.
When falling of the power-supply voltage is detected, the LVRF bit is
set to "1". This bit is cleared by "0" at write. And even if "1" is written
in this bit, the LVRF bit is no effect.
This bit is not initialized in internal reset, and it is initialized only by
the external reset input.
Note: This bit should write "0".
When the counter of CPU operating detecting function overflows,
the CPUF bit is set to "1".
This bit is cleared by "0" at write. And even if "1" is written in this bit,
the CPUF bit is no effect.
This bit is not initialized in internal reset, and it is initialized only by
the external reset input.
Function
377