Block Diagram Of Lin-Uart - Fujitsu F2MCTM-16LX Hardware Manual

Block Diagram of LIN-UART

CLK
SCKn
Pin
SINn
Restart reception
Pin
reload counter
Over-
sampling
unit
Internal signal
LIN break/
to capture
SynchField
detection
2
To EI OS
PE
ORE
FRE
SSRn
RDRF
register
TDRE
BDS
RIE
TIE
n = 0, 1
Figure 20.2-1 Block Diagram of LIN-UART
OTO,
EXT,
REST
Transmission clock
Reload
Reception clock
counter
Reception
control circuit
Start bit
detection
circuit
Received bit
counter
Received
parity counter
Reception
shift register
circuit
Error
detection
RDRn
PE
ORE
FRE
PEN
MD1
MD0 P
SBL
OTO
SMRn
EXT
CL
register
REST
A/D
CRE
UPCL
USCKE RXE
USOE TXE
Transmission
control circuit
Transmission
start circuit
Transmission
TDRE
bit counter
Transmission
parity counter
RDRF
SINn
Transmission
shift register
Transmission
start
TDRn
LBD
Internal data bus
LBIE
LBD
LBL1
SCRn ESCRn
LBL0
register register
SOPE
SIOP
CCO
SCES
CHAPTER 20 LIN-UART
PE ORE FRE
TIE
RIE
LBIE
Interrupt
LBD
generation
circuit
RBI
TBI
Reception
IRQ
Transmission
IRQ
SOTn
Pin
SOTn
SINn
LIN break
generation
circuit
Bus idle
LBR
detection
LBL1
circuit
LBL0
RBI
TBI
LBR
MS
ECCRn
SCDE
SSM
RBI
TBI
387