Fujitsu F2MCTM-16LX Hardware Manual page 110

CHAPTER 5 CLOCKS
Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls the
operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is
affected by switching between the main clock, the PLL clock and the subclock (clock mode) and by a
change in the PLL clock multiplication ratio. Since some peripheral functions receive frequency-divided
output from the timebase timer, a peripheral unit can select the clock best suited for this operation. Figure
5.1-1 shows the clock supply map.
X0A
Pin
Clock
X1A
generator
Pin
X0
Pin
Clock
X1
generator
Pin
Internal
CR oscillation
clock
Clock supervisor function
HCLK : Oscillation clock
MCLK : Main clock
PCLK : PLL clock
SCLK : Sub clock
f : Machine clock
f c : CAN0 to CAN2 clock
94
Figure 5.1-1 Clock Supply Map
Watch timer
Timebase timer
Clock control 1 2 3
block
PLL multiplication circuit
PCLK(PLL clock)
Clock
4/2-divided
selector
SCLK (sub clock)
Clock
Clock selector
2-divided
selector
HCLK
(oscillation clock)
Peripheral function
4
4
Watchdog timer
8/16-bit
PPG timer C to F
4 6
16-bit
reload timer 2, 3
Clock selector CAN1
f c
A/D converter (16ch)
UART0 to 1+
f
serial I/O
(machine clock)
CPU
Input capture 0 to 3
4 Oscillation stabilization
wait control
Pin PPGC to F
Pin TIN2, TIN3
Pin TOT0 to 3
Pin RX1
Pin TX1
Pin AN0 to AN15
Pin SCK0, SCK1
Pin SIN0, SIN1
Pin SOT0, SOT1
I/O timer
Free-run timer 0,1
Pin IN0 to IN3