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CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Table 22.3-1 Functions of Address Detection Control Register (PACSR0)
bit7,
bit6
bit5
bit4
bit3
bit2
bit1
bit0
510
Bit Name
Reserved: reserved bits
Always set to 0.
AD2E:
The address match detection operation with the detect address setting register 2
Address match detec-
(PADR2) is enabled or disabled.
tion enable bit 2
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
Reserved: reserved bit
Always set to 0.
AD1E:
The address match detection operation with the detect address setting register 1
Address match
(PADR1) is enabled or disabled.
detection enable bit 1
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
Reserved: reserved bit
Always set to 0.
AD0E:
The address match detection operation with the detect address setting register 0
Address match
(PADR0) is enabled or disabled.
detection enable bit 0
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
Reserved: reserved bit
Always set to 0.
When the value of detect address setting registers 2 (PADR2) matches with
the value of address latch at enabling the address match detection operation
(AD2E = 1), the INT9 instruction is immediately executed.
When the value of detect address setting registers 1 (PADR1) matches with
the value of address latch at enabling the address match detection operation
(AD1E = 1), the INT9 instruction is immediately executed.
When the value of detect address setting registers 0 (PADR0) matches with
the value of address latch at enabling the address match detection operation
(AD0E = 1), the INT9 instruction is immediately executed.
Function
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