Fujitsu F2MCTM-16LX Hardware Manual page 586

APPENDIX
Table A-1 I/O Map (3/5)
Address
00004B
Reserved
H
00004C
PPGE operation mode control register
H
00004D
PPGF operation mode control register PPGCF
H
00004E
PPGE/F count clock selection register PPGEF
H
00004F
Reserved
H
000050
Input capture control status 0/1
H
000051
Input capture edge 0/1
H
000052
Input capture control status 2/3
H
000053
Input capture edge 2/3
H
000054 to
H
Reserved
000063
H
000064
Timer control status 2
H
000065
Timer control status 2
H
000066
Timer control status 3
H
000067
Timer control status 3
H
000068
A/D control status 0
H
000069
A/D control status 1
H
00006A
A/D data 0
H
00006B
A/D data 1
H
00006C
ADC setting 0
H
00006D
ADC setting 1
H
Detection reset control register of
00006E
H
low-voltage/CPU operation
00006F
ROM mirror function select
H
000070 to
H
Reserved
00007F
H
000080 to
H
Reserved for CAN interface. (For more information, see Table 21.3-1 .)
00008F
H
000090 to
H
Reserved
00009D
H
00009E
Address detection control register0
H
570
Register Abbreviation
PPGCE
ICS01
ICE01
ICS23
ICE23
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
LVRC
ROMM
PACSR0
Access Peripheral
W, R/W
16-bit
W, R/W
PPGE/F
R/W
R/W
Input Capture 0/1
R/W, R
R/W
Input Capture 2/3
R
R/W
16-bit Reload Timer
2
R/W
R/W
16-bit Reload Timer
3
R/W
R/W
R/W, W
R
A/D Converter
R
R/W
R/W
Detection Reset of
R/W, W Low-voltage/CPU
Operation
W ROM Mirror
Address Match
R/W
Detection 0
Initial value
0 X 0 0 0 XX1
B
0 X 0 0 0 0 0 1
B
0 0 0 0 0 0 X 0
B
0 0 0 0 0 0 0 0
B
XXX0X0XX
B
0 0 0 0 0 0 0 0
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
XXXX 0 0 0 0
B
0 0 0 0 0 0 0 0
B
XXXX 0 0 0 0
B
0 0 0 XXXX 0
B
0 0 0 0 0 0 0 X
B
0 0 0 0 0 0 0 0
B
XXXXXX 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 1 1 1 0 0 0
B
XXXXXXX1
B
0 0 0 0 0 0 0 0
B