Block Diagram Of Mb90360 Series; Block Diagram Of Evaluation Chip - Fujitsu F2MCTM-16LX Hardware Manual

1.2

Block Diagram of MB90360 series

Figure 1.2-3 shows a block diagram of the MB90360.

Block Diagram of Evaluation Chip

Figure 1.2-1 Block Diagram of Evaluation Chip (MB90V340A-101/102)
X0, X1
X0A, X1A *
RST
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
AV
CC
AV
SS
AN23 to AN0
AVRH
AVRL
ADTG
DA01, DA00
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
*: Support MB90V340A-102 only
Clock
control
2
F MC-16LX core
RAM 30KB
Prescaler
(5 channels)
UART
(5 channels)
8-/10-bit
A/D
converter
24 channels
10-bit
D/A
converter
2 channels
8-/16-bit
PPG
16 channels
2
I C
interface
2channels
DMA
CHAPTER 1 OVERVIEW
16-bit
FRCK0
I/O timer 0
Input
capture
IN7 to IN0
8 channels
Output
compare
OUT7 to OUT0
8 channels
16-bit
I/O timer 1
FRCK1
CAN
RX2 to RX0
controller
TX2 to TX0
3 channels
16-bit
TIN3 to TIN0
reload
timer TOT3 to TOT0
4 channels
AD15 to AD00
A23 to A16
External
bus
DTP/
INT15 to INT8
external
(INT15R to INT8R)
interrupt
INT7 to INT0
Clock
monitor
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
CKOT
9