A/D Control Status Register (High) (Adcs1) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 18 8-/10-BIT A/D CONVERTER
18.3.1

A/D Control Status Register (High) (ADCS1)

The A/D control status register (High) (ADCS1) provides the following settings:
• Starting A/D conversion function by software
• Selecting start trigger for A/D conversion
• Storing A/D conversion results in A/D data register to enable or disable interrupt
request
• Storing A/D conversion results in A/D data register to check and clear interrupt
request flag
• Pausing A/D conversion and checking state during conversion
A/D Control Status Register (High) (ADCS1)
15
14
Address
000069
BUSY INT INTE PAUS STS1 STS0 STRT
H
R/W R/W
R/W : Read/Write
W
−
X
346
Figure 18.3-2 A/D Control Status Register (High) (ADCS1)
13 12 11 10 9
R/W R/W R/W R/W W
: Write only
: Undefined bit
: Indeterminate
: Reset value
8
Reset value
−
0000000X
B
−
bit8
-
Read value is always 1.
bit9
STRT A/D conversion software starting bit
Not starting A/D conversion function
0
1
Starting A/D conversion function
bit11 bit10
A/D conversion starting trigger select bit
STS1 STS0
0 0
Starting software
0 1 Starting software or external trigger
1 0
Starting software
1 1
Starting software or external trigger
bit12
Suspended flag bit
(This bit is enabled only when EI
PAUS
Read
Conversion is not suspended.
0
1
Conversion is suspended.
bit13
Interrupt request enable bit
INTE
Interrupt request disable
0
Interrupt request enable
1
bit14
Interrupt request flag bit
INT
Read
A/D conversion not terminated
0
1 A/D conversion terminated
bit15
A/D conversion-on flag bit
BUSY
Read
A/D conversion terminated
(inactive state)
0
1 A/D conversion in operation
Undefined bit
2
OS is used.)
Write
Clear to "0".
No effect.
Write
Clear to "0"
No effect
Write
Terminates A/D conversion
forcibly
No effect