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Fujitsu MB90360 series Manuals
Manuals and User Guides for Fujitsu MB90360 series. We have
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Fujitsu MB90360 series manual available for free PDF download: Hardware Manual
Fujitsu MB90360 series Hardware Manual (682 pages)
16-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Computer Hardware
| Size: 13.3 MB
Table of Contents
Table of Contents
9
Chapter 1 Overview
17
Overview of MB90360
18
Product Overview
21
Block Diagram of MB90360 Series
25
Block Diagram of Evaluation Chip
25
Block Diagram of Flash/Mask Rom Version
27
Package Dimensions
28
Pin Assignment
29
Pin Functions
30
Input-Output Circuits
33
Handling Device
37
Chapter 2 Cpu
43
Outline of the CPU
44
Memory Space
45
Ram Area
46
I/O Area
46
Memory Map
48
Linear Addressing
49
Bank Addressing Types
50
Multi-Byte Data in Memory Space
52
Registers
53
Accumulator (A)
56
User Stack Pointer (USP) and System Stack Pointer (SSP)
57
Processor Status (PS)
58
Register Bank Pointer (Rp)
59
Program Counter (PC)
61
Register Bank
62
Prefix Codes
64
Bank Select Prefix
64
Common Register Bank Prefix (Cmr)
65
Flag Change Disable Prefix (Ncc)
65
Interrupt Disable Instructions
67
Precautions for Use of "DIV A, Ri" and "DIVW A, Rwi" Instructions
68
Chapter 3 Interrupts
71
Outline of Interrupts
72
Software Interrupts
73
Interrupt Vector
75
Interrupt Control Registers (ICR)
77
Interrupt Flow
81
Hardware Interrupts
83
Structure of Hardware Interrupt
83
Hardware Interrupt Operation
84
Occurrence and Release of Hardware Interrupt
85
Multiple Interrupts
87
Software Interrupts
88
Structure of Software Interrupts
88
Software Interrupt Operation
88
Extended Intelligent I/O Service (EI 2 OS)
90
Extended Intelligent I/O Service Descriptor (ISD)
92
Buffer Address Pointer (Bap)
93
EI 2 os Status Register (ISCS)
94
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI 2 OS)
95
Exceptions
98
Execution of an Undefined Instruction
98
Chapter 4 Delayed Interrupt Generation Module
99
Overview of Delayed Interrupt Generation Module
100
Block Diagram of Delayed Interrupt Generation Module
101
Interrupt Number
101
Configuration of Delayed Interrupt Generation Module
102
Delayed Interrupt Request Generate/Cancel Register (DIRR)
103
Explanation of Operation of Delayed Interrupt Generation Module
104
Precautions When Using Delayed Interrupt Generation Module
105
Program Example of Delayed Interrupt Generation Module
106
Chapter 5 Clocks
107
Clocks
108
Block Diagram of the Clock Generation Block
111
Register of Clock Generation Block
113
Clock Selection Register (CKSCR)
114
Pll Clock Multiplier
114
Pll/Subclock Control Register (PSCCR)
117
Clock Mode
119
Clock Mode Transition
119
Selection of a Pll Clock Multiplier
120
Chapter 5 Clocks
121
Oscillation Stabilization Wait Interval
123
Connection of an Oscillator or an External Clock to the Microcontroller
124
Chapter 6 Clock Supervisor
125
Overview of Clock Supervisor
126
Block Diagram of Clock Supervisor
127
Clock Supervisor Control Register (CSVCR)
129
Operating Mode of Clock Supervisor
131
Operating Mode in Initialized State
131
Sub-Clock Mode
132
Sub-Clock Mode with External Single Clock Product
132
Reset Check by Clock Supervisor
133
Chapter 7 Resets
135
Resets
136
Reset Cause and Oscillation Stabilization Wait Times
139
Reset Causes and Oscillation Stabilization Wait Times
139
Oscillation Stabilization Wait and Reset State
140
External Reset Pin
141
Block Diagrams of the External Reset Pin
141
Reset Operation
142
Overview of Reset Operation
142
Mode Fetch
143
Reset Cause Bits
144
Notes about Reset Cause Bits
147
Status of Pins in a Reset
148
Status of Pins During a Reset
148
Status of Pins after Mode Data Is Read
148
Chapter 8 Low-Power Consumption Mode
149
Overview of Low-Power Consumption Mode
150
Standby Mode
151
Block Diagram of the Low-Power Consumption Control Circuit
153
Low-Power Consumption Mode Control Register (LPMCR)
155
CPU Intermittent Operation Mode
158
Standby Mode
159
Sleep Mode
161
Return from Watch Mode
164
Switching to the Watch Mode
164
Watch Mode
164
Return from Timebase Timer Mode
166
Switching to the Timebase Timer Mode
166
Timebase Timer Mode
166
Stop Mode
168
Status Change Diagram
171
Status of Pins in Standby Mode and During Hold and Reset
172
Usage Notes on Low-Power Consumption Mode
173
Transition to Standby Mode
173
Notes on the Transition to Standby Mode
173
Clock Mode Switching
174
Chapter 9 Memory Access Modes
177
Outline of Memory Access Modes
178
Mode Pins
179
Mode Data
180
Memory Space in each Bus Mode
181
Chapter 10 I/O Ports
183
I/O Ports
184
I/O Port Registers
185
Port Data Register (PDR)
186
Port Direction Register (DDR)
188
Block Diagram of Pull-Up Control Register (Pucr)
190
Pull-Up Control Register (PUCR)
190
Analog Input Enable Register (ADER)
191
Input Level Select Register
192
Chapter 11 Timebase Timer
195
Overview of Timebase Timer
196
Block Diagram of Timebase Timer
198
Configuration of Timebase Timer
200
List of Registers and Reset Values of Timebase Timer
200
Generation of Interrupt Request from Timebase Timer
200
Timebase Timer Control Register (TBTC)
201
Interrupt of Timebase Timer
203
Explanation of Operations of Timebase Timer Functions
204
Precautions When Using Timebase Timer
208
Program Example of Timebase Timer
209
Chapter 12 Watchdog Timer
211
Overview of Watchdog Timer
212
Functions of Watchdog Timer
212
Configuration of Watchdog Timer
215
Block Diagram of Watchdog Timer
215
Watchdog Timer Registers
217
Watchdog Timer Control Register (WDTC)
218
Explanation of Operations of Watchdog Timer Functions
220
Precautions When Using Watchdog Timer
223
Program Examples of Watchdog Timer
224
CHAPTER 13 16-Bit I/O TIMER
226
Overview of 16-Bit I/O Timer
226
Module Configuration of 16-Bit I/O Timer
226
Functions of 16-Bit I/O Timer
226
Block Diagram of 16-Bit I/O Timer
227
Details of Pins and Interrupt Number
228
Block Diagram of 16-Bit Free-Run Timer
229
Block Diagram of Input Capture
230
Configuration of 16-Bit I/O Timer
232
Pins of 16-Bit I/O Timer
232
Generation of Interrupt Request from 16-Bit I/O Timer
232
Timer Control Status Register (Upper) (TCCSH)
233
Timer Control Status Register (Lower) (TCCSL)
234
Timer Data Register (TCDT)
236
Input Capture Control Status Registers (ICS)
237
Input Capture Register (IPCP)
239
Input Capture Edge Register (ICE)
240
Interrupts of 16-Bit I/O Timer
243
Explanation of Operation of 16-Bit Free-Run Timer
245
Explanation of Operation of Input Capture
247
Setting of Input Capture
247
Precautions When Using 16-Bit I/O Timer
249
Program Example of 16-Bit I/O Timer
250
Chapter 14 16-Bit Reload Timer
253
Overview of the 16-Bit Reload Timer
254
Operation Modes of 16-Bit Reload Timer
254
Internal Clock Mode
254
Operation at Underflow
255
Block Diagram of 16-Bit Reload Timer
256
Configuration of 16-Bit Reload Timer
258
Pins of 16-Bit Reload Timer
258
Bit Reload Timer Registers and Reset Value
259
Timer Control Status Registers (High) (TMCSR:H)
261
Timer Control Status Registers (Low) (TMCSR: L)
263
16-Bit Timer Registers (TMR)
265
16-Bit Reload Registers (TMRLR)
266
Interrupts of 16-Bit Reload Timer
267
Explanation of Operation of 16-Bit Reload Timer
268
Setting of 16-Bit Reload Timer
268
Operating State of 16-Bit Timer Register
269
Operation in Internal Clock Mode
270
Setting of Internal Clock Mode
270
Operation in Event Count Mode
275
Precautions When Using 16-Bit Reload Timer
278
Sample Program of 16-Bit Reload Timer
279
Program Example in Internal Clock Mode
279
Program Example in Event Counter Mode
280
Chapter 15 Watch Timer
283
Overview of Watch Timer
284
Block Diagram of Watch Timer
286
Configuration of Watch Timer
288
List of Registers and Reset Values of Watch Timer
288
Generation of Interrupt Request from Watch Timer
288
Watch Timer Control Register (WTC)
289
Watch Timer Interrupt
291
Explanation of Operation of Watch Timer
292
Setting Operation Clock of Watchdog Timer
293
Program Example of Watch Timer
294
Chapter 16 8-/16-Bit Ppg Timer
297
Overview of 8-/16-Bit PPG Timer
298
Functions of 8-/16-Bit Ppg Timer
298
Operation Modes of 8-/16-Bit Ppg Timer
299
Block Diagram of 8-/16-Bit PPG Timer
301
Channels and Ppg Pins of Ppg Timers
301
Block Diagram for 8-/16-Bit PPG Timer C
302
Block Diagram of 8-/16-Bit Ppg Timer C
302
Block Diagram of 8-/16-Bit PPG Timer D
304
Configuration of 8-/16-Bit PPG Timer
306
Pins of 8-/16-Bit Ppg Timer
306
PPGC Operation Mode Control Register (PPGCC)
308
PPGD Operation Mode Control Register (PPGCD)
310
PPGC/D Count Clock Select Register (PPGCD)
312
PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD)
314
Interrupts of 8-/16-Bit PPG Timer
315
Interrupt of 8-/16-Bit Ppg Timer
315
Explanation of Operation of 8-/16-Bit PPG Timer
316
8-Bit PPG Output 2-Channel Independent Operation Mode
317
16-Bit PPG Output Operation Mode
320
Setting for 16-Bit Ppg Output Operation Mode
320
8+8-Bit PPG Output Operation Mode
323
Setting for 8+8-Bit Ppg Output Operation Mode
323
Precautions When Using 8-/16-Bit PPG Timer
326
Chapter 17 Dtp/External Interrupts
329
Overview of Dtp/External Interrupt
330
Block Diagram of Dtp/External Interrupt
331
Details of Pins and Interrupt Numbers
332
Configuration of Dtp/External Interrupt
333
Dtp/External Interrupt Factor Register (EIRR1)
335
Dtp/External Interrupt Enable Register (ENIR1)
337
Detection Level Setting Register (ELVR1)
339
External Interrupt Factor Select Register (EISSR)
341
Explanation of Operation of Dtp/External Interrupt
343
External Interrupt Function
347
DTP Function
348
Precautions When Using Dtp/External Interrupt
349
Program Example of Dtp/External Interrupt Function
351
Program Example of Dtp Function
352
Chapter 18 8-/10-Bit A/D Converter
355
Overview of 8-/10-Bit A/D Converter
356
Function of 8-/10-Bit A/D Converter
356
Conversion Modes of 8-/10-Bit A/D Converter
356
Block Diagram of 8-/10-Bit A/D Converter
357
Configuration of 8-/10-Bit A/D Converter
360
Pins of 8-/10-Bit A/D Converter
360
Generation of Interrupt from 8-/10-Bit A/D Converter
361
A/D Control Status Register (High) (ADCS1)
362
A/D Control Status Register (Low) (ADCS0)
365
A/D Data Register (ADCR0/ADCR1)
367
A/D Setting Register (ADSR0/ADSR1)
368
Analog Input Enable Register (ADER5, ADER6)
372
Interrupt of 8-/10-Bit A/D Converter
374
Interrupt of A/D Converter
374
Explanation of Operation of 8-/10-Bit A/D Converter
375
Single-Shot Conversion Mode
376
Continuous Conversion Mode
378
Pause-Conversion Mode
380
Operation of Pause-Conversion Mode
381
Conversion Using EI 2 os Function
382
A/D-Converted Data Protection Function
383
Precautions When Using 8-/10-Bit A/D Converter
385
Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
388
Overview of Low Voltage/Cpu Operating Detection Reset Circuit
388
Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
389
Configuration of Low Voltage/Cpu Operating Detection Reset Circuit
390
Low Voltage/Cpu Operating Detection Reset Circuit Register
392
Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
393
Operating of Low Voltage/Cpu Operating Detection Reset Circuit
394
Notes on Using Low Voltage/Cpu Operating Detection Reset Circuit
395
Sample Program for Low Voltage/Cpu Operating Detection Reset Circuit
396
Chapter 20 Lin-Uart
397
Overview of LIN-UART
398
Lin-Uart Functions
398
Configuration of LIN-UART
402
Block Diagram of Lin-Uart
403
LIN-UART Pins
407
Block Diagram of Lin-Uart Pins
407
LIN-UART Registers
408
Serial Control Register (SCR)
409
LIN-UART Serial Mode Register (SMR)
411
Serial Status Register (SSR)
413
Reception and Transmission Data Register (RDR/TDR)
415
Reception Data Register (Rdr)
415
Transmission Data Register (Tdr)
416
Extended Status/Control Register (ESCR)
417
Extended Communication Control Register (ECCR)
419
Baud Rate Generator Register 0 and 1 (BGR0/1)
421
LIN-UART Interrupts
422
Reception Interrupt Generation and Flag Set Timing
425
Transmission Interrupt Generation and Flag Set Timing
427
LIN-UART Baud Rates
429
Lin-Uart Baud Rate Selection
429
Setting the Baud Rate
431
Restarting the Reload Counter
434
Function of Reload Counter
434
Operation of LIN-UART
436
Inter-Cpu Connection Method
437
Synchronization Methods
437
Operation in Asynchronous Mode (Op. Modes 0 and 1)
438
Operation in Synchronous Mode (Operation Mode 2)
442
Operation with LIN Function (Operation Mode 3)
445
Direct Access to Serial Pins
448
Lin-Uart Direct Pin Access
448
Bidirectional Communication Function (Normal Mode)
449
Master-Slave Communication Function (Multiprocessor Mode)
451
LIN Communication Function
454
Sample Flowcharts for LIN-UART in LIN Communication (Operation Mode 3)
455
Lin-Uart as Lin Master Device
455
Notes on Using LIN-UART
457
Chapter 21 Can Controller
459
Features of CAN Controller
460
Block Diagram of CAN Controller
461
List of Overall Control Registers
462
List of Message Buffers (ID Registers)
464
Classifying CAN Controller Registers
468
Configuration of Control Status Register (CSR)
469
Function of Control Status Register (CSR)
470
Correspondence between Node Status Bit and Node Status
472
Notes on Using Bus Operation Stop Bit (HALT = 1)
473
Last Event Indicator Register (LEIR)
474
Receive and Transmit Error Counters (RTEC)
477
Bit Timing Register (BTR)
478
Prescaler Setting by Bit Timing Register (BTR)
479
Prescaler Settings
479
Message Buffer Valid Register (BVALR)
481
IDE Register (IDER)
482
Transmission Request Register (TREQR)
483
Transmission RTR Register (TRTRR)
484
Remote Frame Receiving Wait Register (RFWTR)
485
Transmission Cancel Register (TCANR)
486
Transmission Complete Register (TCR)
487
Transmission Interrupt Enable Register (TIER)
488
Reception Complete Register (RCR)
489
Remote Request Receiving Register (RRTRR)
490
Receive Overrun Register (ROVRR)
491
Reception Interrupt Enable Register (RIER)
492
Acceptance Mask Select Register (AMSR)
493
Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
495
Message Buffers
497
ID Register X (X = 0 to 15) (Idrx)
499
DLC Register X (X = 0 to 15) (Dlcrx)
501
Data Register X (X = 0 to 15) (Dtrx)
502
Transmission of CAN Controller
504
Starting Transmission of Can Controller
504
Transmission Flowchart of Can Controller
505
Reception of CAN Controller
506
Storing Received Message
506
Receive Overrun
507
Completing Reception
508
Reception Flowchart of CAN Controller
509
Reception Flowchart of the Can Controller
509
How to Use CAN Controller
510
Setting Bit Timing
510
Procedure for Transmission by Message Buffer (X)
512
Procedure for Reception by Message Buffer (X)
514
21.11 Setting Configuration of Multi-Level Message Buffer
516
21.12 Setting the CAN Direct Mode Register
518
21.13 Precautions When Using CAN Controller
519
Caution for Disabling Message Buffers by Bval Bits
519
Setting of Can Direct Mode
520
Chapter 22 Address Match Detection Function
521
Overview of Address Match Detection Function
522
Block Diagram of Address Match Detection Function
523
Configuration of Address Match Detection Function
524
Address Detection Control Register (PACSR0/PACSR1)
525
Detect Address Setting Registers (PADR0 to PADR5)
529
Explanation of Operation of Address Match Detection Function
532
Example of Using Address Match Detection Function
533
Flow of Patch Processing for Patch Program
536
Program Example of Address Match Detection Function
538
Chapter 23 Rom Mirroring Module
541
Overview of ROM Mirroring Function Select Module
542
Access to Ff Bank by Rom Mirroring Function
542
ROM Mirroring Function Select Register (ROMM)
544
Chapter 24 512K-Bit Flash Memory
545
Overview of 512K-Bit Flash Memory
546
K-Bit Flash Memory Features
546
Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory
547
Sector Configuration of the 512K-Bit Flash Memory
547
Write/Erase Modes
549
Flash Memory Mode
549
Flash Memory Control Status Register (FMCS)
551
Starting the Flash Memory Automatic Algorithm
554
Confirming the Automatic Algorithm Execution State
555
Hardware Sequence Flags
555
Data Polling Flag (DQ7)
557
Toggle Bit Flag (DQ6)
558
Timing Limit Exceeded Flag (DQ5)
559
Detailed Explanation of Writing to and Erasing Flash Memory
560
Detailed Explanation of Flash Memory Write/Erase
560
Setting the Flash Memory to the Read/Reset State
561
Setting the Read/Reset State
561
Writing Data
562
Flash Memory
562
Erasing All Data (Erasing Chips)
564
Notes on Using 512K-Bit Flash Memory
566
Flash Security Feature
567
How to Disable the Flash Security Feature
567
How to Enable the Flash Security Feature
567
Chapter 25 Examples of Mb90F362/T(S), Mb90F367/T(S)Serial Programming Connection
569
Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S)
570
Example of Serial Programming Connection (User Power Supply Used)
573
Example of Serial Programming Connection (Power Supplied from Programmer)
575
Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)
577
Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)
579
Chapter 26 Rom Security Function
581
Overview of ROM Security Function
582
Appendix
583
APPENDIX A I/O Maps
584
APPENDIX B Instructions
592
Instruction Types
593
B.1 Instruction Types
593
Addressing
594
B.2 Addressing
594
Direct Addressing
596
B.3 Direct Addressing
596
Indirect Addressing
602
B.4 Indirect Addressing
602
Execution Cycle Count
609
Effective Address Field
612
How to Read the Instruction List
613
F 2 MC-16LX Instruction List
616
Instruction Map
630
B.9 Instruction Map
630
Structure of Instruction Map
630
APPENDIX C Timing Diagrams in Flash Memory Mode
652
Chip Erase/Sector Erase Command Sequence
655
Toggle Bit
656
Ry/By Timing During Writing/Erasing
657
Rst and Ry/By Timing
657
Enable Sector Protect/Verify Sector Protect
658
Temporary Sector Protect Cancellation
659
APPENDIX D List of Interrupt Vectors
660
Pll Clock Multiplier/Prescaler Settings
676
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