Lin-Uart Interrupts - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 20 LIN-UART
20.5

LIN-UART Interrupts

LIN-UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the following causes:
• Receive data is set in the reception data register (RDR), or a reception error occurs.
• Transmission data is transferred from the transmission data register (TDR) to the
transmission shift register and transmission is started.
• A LIN break is detected.
The extended intelligent I/O service (EI
LIN-UART Interrupts
Table 20.5-1 shows the interrupt control bits and interrupt cause of the LIN-UART.
Table 20.5-1 Interrupt Control Bits and Interrupt Cause of LIN-UART
Reception/ Interrupt
transmission request
/ICU flag bit
Reception RDRF
ORE
FRE
PE
LBD
Transmission TDRE
Input Capture ICP0/ICP1
ICP0/ICP1
: Used bit
×: Unused bit
∆: Only available if ECCR/SSM = 1
406
2
OS) is available for these interrupts.
Flag Operation mode
register
0 1
SSR
SSR
SSR
×
SSR
× ×
ESCR
SSR
× ×
ICS01
× ×
ICS01
Interrupt cause
2 3
Receive data is
written to RDR.
Overrun error
∆
Framing error
∆ ×
Parity error
×
LIN Synch break
detected
TDR empty
×
1st falling edge of
LIN synch field
×
5th falling edge of
LIN synch field
Interrupt How to clear the
cause enable interrupt request
bit
SSR:RIE Receive data is
read.
"1" is written to
clear reception
error flag bit
(SCR: CRE).
ESCR:LBIE "0" is written to
ESCR: LBD.
SSR:TIE Write data to
TDR
ICS01: Disable ICP0/
ICE0/ICE1 ICP1 temporary