Transmission Complete Register (Tcr) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.15

Transmission Complete Register (TCR)

At completion of transmission by the message buffer (x), the corresponding TCx
becomes 1.
If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt
occurs.
Register Configuration
Figure 21.4-15 Configuration of the Transmission Complete Register (TCR)
Address
CAN1: 000087
Address
CAN1: 000086
R/W : Read/Write
X : Undefined
Register Function
Conditions for TCx = 0
• Write 0 to TCx.
• Write 1 to TREQx of the transmission request register (TREQR).
After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored.
1 is read when a Read Modify Write instruction is performed.
Note:
If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.
bit15 bit14 bit13
TC15 TC14 TC13
H
R/W R/W R/W
bit7 bit6 bit5
TC7 TC6 TC5
H
R/W R/W R/W
bit12 bit11 bit10
TC12 TC11 TC10
R/W R/W R/W
bit4 bit3 bit2
TC4 TC3 TC2
R/W R/W R/W
bit9 bit8 TCR1(Upper)
TC9 TC8 Reset value
0 0 0 0 0 0 0 0
R/W R/W
bit1 bit0 TCR1(Lower)
TC1 TC0 Reset value
0 0 0 0 0 0 0 0
R/W R/W
B
B
471