Fujitsu F2MCTM-16LX Hardware Manual page 654

APPENDIX
Write, Data Polling, Read (CE control)
to
AQ18 AQ0
WE
OE
CE
to
DQ7 DQ0
PA : Write address
PD : Write data
DQ : Reverse output of write data
7
D : Output of write data
OUT
Note:
• Describes the last 2-bus cycle of 4-bus cycle sequences.
• "Fx" in "FxAAAA" described as address is any of F.
638
Figure C-3 Timing Diagram for Write Access (CE control)
3rd bus cycle
PA
FxAAAA
H
t
WC
t
AS
t
WH
t
GHWL
t
CP
t
CPH
t
WS
t
DH
A0
H
t
DS
Data polling
t
AH
t
WHWH1
PD
DQ7
PA
Dout