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CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels
ILM2
0
0
0
0
1
1
1
1
[bit 11, bit 3] ISE (extended intelligent I/O service enable bits)
The ISE bit is readable and writable. In response to an interrupt request, EI
set in the ISE bit and an interrupt sequence is activated when '0' is set in the ISE bit. Upon completion
of EI
function, the ISE bit must be set to '0' on the software side.
Upon a reset, the ISE bit is initialized to '0'.
62
ILM1
0
0
1
1
0
0
1
1
2
OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI
ILM0
0
0 (strongest)
1
1
0
2
1
3
0
4
1
5
0
6 (weakest)
1
7 (no interrupt)
Level
2
OS is activated when '1' is
2
OS
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