Fujitsu F2MCTM-16LX Hardware Manual page 112

CHAPTER 5 CLOCKS
Oscillation clock generation circuit
This circuit generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external
clock to the high-speed oscillation pins.
Sub-clock generation circuit
This circuit generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to the
low-speed oscillation pins (X0A, X1A).
PLL multiplier circuit
This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector.
Clock selector
From among the main clock, five different PLL clocks and subclock, the clock selector selects the clock
that is supplied to the CPU and peripheral function.
Clock selection register (CKSCR)
The clock selection register is used to switch between the oscillation clock and PLL clock and between the
main clock and sub-clock, also used to select an oscillation stabilization wait interval and a PLL clock
multiplier.
PLL/Subclock Control Register (PSCCR)
The PLL/subclock control register is used to select multiplication ratio of the PLL (CS2 bit in this register
in addition to CS1 and CS0 bits in the CKSCR register) and to specify division ratio (1/4 or 1/2) of the
subclock.
Oscillation stabilization wait interval selector
This oscillation stabilization wait interval selector selects an oscillation stabilization wait interval for the
oscillation clock. Selection is made from among four different timebase timer outputs.
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