Receive And Transmit Error Counters (Rtec) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.6

Receive and Transmit Error Counters (RTEC)

The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
Register Configuration
Figure 21.4-5 Configuration of the Receive and Transmit Error Counters
Address
CAN1: 007D05
Address
CAN1: 007D04
R : Read only
Register Function
Table 21.4-5 Function of Each Bit of the Receive and Transmit Error Counters (RTEC)
Bit Name
bit15 TEC7 to TEC0:
to Transmit error counter
bit8 bits
bit7 REC7 to REC0:
to Receive error counter
bit0 bits
bit15 bit14 bit13
TEC7 TEC6 TEC5
H
R R R
bit7 bit6 bit5
REC7 REC6 REC5
H
R R R
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Bus Off is indicated
for the node status (NS1 and NS0 of control status register CSR = 11).
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Error Passive is
indicated for the node status (NS1 and NS0 of control status register CSR = 10).
bit12 bit11 bit10
TEC4 TEC3 TEC2 TEC1
R R R
bit4 bit3 bit2
REC4 REC3 REC2 REC1
R R R
Function
bit9 bit8 RTEC1(Upper)
TEC0 Reset value
0 0 0 0 0 0 0 0
R R
bit1 bit0 RTEC1(Lower)
REC0 Reset value
0 0 0 0 0 0 0 0
R R
B
B
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