Address Detection Control Register (Pacsr0/Pacsr1) - Fujitsu F2MCTM-16LX Hardware Manual

22.3.1

Address Detection Control Register (PACSR0/PACSR1)

The address detection control register enables or disables output of an interrupt at an
address match. When an address match is detected when output of an interrupt at an
address match is enabled, the INT9 interrupt is generated.
Address Detection Control Register 0 (PACSR0)
Figure 22.3-2 Address Detection Control Register 0 (PACSR0)
7
Address
Re-
0 0 0 0 9 E
H
served served
R/W R/W
R/W : Read/Write
: Reset value
6 5 4 3 2 1
Re- Re- Re-
AD2E AD1E AD0E
served served
R/W R/W R/W R/W R/W
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
0
Reset value
Re-
0 0 0 0 0 0 0 0
B
served
bit 0
R/W
Reserved
0 Always set to "0"
bit 1
AD0E Address match detection enable bit 0
0 Disables address match detection in PADR0
1 Enables address match detection in PADR0
bit 2
Reserved
0 Always set to "0"
bit 3
AD1E Address match detection enable bit 1
0 Disables address match detection in PADR1
1 Enables address match detection in PADR1
bit 4
Reserved
0 Always set to "0"
bit 5
AD2E Address match detection enable bit 2
0 Disables address match detection in PADR2
1 Enables address match detection in PADR2
bit 6
Reserved
0 Always set to "0"
bit 7
Reserved
0 Always set to "0"
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
509