Fujitsu F2MCTM-16LX Hardware Manual page 206

CHAPTER 11 TIMEBASE TIMER
Operation as Oscillation Stabilization Wait Time Timer
The timebase timer can be used as the oscillation stabilization wait time timer for the main clock and PLL
clock.
The oscillation stabilization wait time is the time elapsed from when the timebase timer counter increments
from "0" until the set oscillation stabilization wait time select bit overflows (carrying).
Table 11.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer.
Table 11.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase
Writing "0" to timebase timer
counter clear bit (TBTC: TBR)
Reset
Power-on reset
Watchdog reset
External reset
Low voltage detection reset
CPU operation detection reset
Clock supervisor reset
Software reset
Switching clock mode
Main clock → PLL clock
(CKSCR: MCS=1 → 0)
Main clock → sub clock
(CKSCR: SCS=1 → 0)
Sub clock → main clock
(CKSCR: SCS=0 → 1)
Sub clock → PLL clock
(CKSCR: MCS=0, SCS=0 → 1)
PLL clock → main clock
(CKSCR: MCS=0 → 1)
PLL clock → sub clock
(CKSCR: MCS=0, SCS=1 → 0)
190
Timer (1/2)
Operation Counter TBOF
clear clear
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
None
None
None
Transition to PLL clock mode after
oscillation stabilization wait time of
PLL clock completed
Transition to sub clock mode after
oscillation stabilization wait time of
sub clock completed
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
Transition to PLL clock mode after
oscillation stabilization wait time of
main clock completed
None
None
Oscillation stabilization wait time