Fujitsu F2MCTM-16LX Hardware Manual page 663

Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt cause
UART 1 RX
UART 1 TX
Reserved
Reserved
Flash memory
Delayed interrupt generation module
2
Y1: An EI OS interrupt clear signal or EI
2
Y2: An EI OS interrupt clear signal or EI
2
N: An EI OS interrupt clear signal does not clear the interrupt request flag.
Note:
For a peripheral module having two interrupt causes for one interrupt number, an EI
signal clears both interrupt request flags.
When EI
number.
2
EI OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused
while EI
interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt
must be disabled.
2
EI OS clear
Y2
Y1
N
N
N
N
2
OS register read access clears the interrupt request flag.
2
OS register read access clears the interrupt request flag. A stop request is issued.
2 2
OS ends, an EI OS clear signal is sent to every interrupt flag assigned to each interrupt
2
OS is enabled. This means that an EI
APPENDIX D List of Interrupt Vectors
Interrupt vector
DMA
channel
number
Number
FFFF68
#37
H
FFFF64
#38
H
FFFF60
#39
H
FFFF5C
#40
H
FFFF58
#41
H
FFFF54
#42
H
2
OS descriptor that should essentially be specific to each
Interrupt control register
ICR Address
0000BD
ICR13
H
0000BE
ICR14
H
0000BF
ICR15
H
2
OS interrupt clear
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