Fujitsu F2MCTM-16LX Hardware Manual page 424

CHAPTER 20 LIN-UART
LIN Synchronization Field Edge Detection Interrupts
This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave. After LIN synch break
detection, the internal signal is set to "1" at first falling edge of the LIN synch field and to "0" after fifth
falling edge. When the internal signal is set in the capture side to be inputted to capture (ICV0/1) and to be
detected both edges, the interrupt occurs if the capture interrupt is enabled. The difference of the count
values detected in the capture is serial clock 8 bits for master, and new baud rate can be calculated.
When the falling edge of the start bit is detected, the reload counter restarts automatically.
LIN-UART Interrupts and EI
Table 20.5-2 LIN-UART Interrupts and EI
Channel
LIN-UART0 reception
LIN-UART0 transmission
LIN-UART1 reception
LIN-UART1 transmission
*1: Usable when ICR12 and ICR13 or interrupt causes that share an interrupt vector are not used. Provided with a function
that detects a LIN-UART reception error and stops EI
*2: Usable when ICR12 and ICR13 or interrupt causes that share an interrupt vector are not used.
2
LIN-UART EI OS functions
LIN-UART has a circuit for operating EI
interrupts.
For Reception
2
EI OS can be used if other interrupt is not enabled because the UART shares the interrupt control registers
with transmission interrupt and other UART.
For Transmission
LIN-UART shares the interrupt control registers with the LIN-UART reception interrupts and other UART.
Therefore, EI
408
2
OS
2
OS
Interrupt Interrupt control register
number
Register
name
#35(23 ) ICR12
H
#36(24 ) ICR12
H
#37(25 ) ICR13
H
#38(26 ) ICR13
H
2
OS can be started up only when no LIN-UART reception interrupts are used.
Vector table address
Address Lower
0000BC FFFF70
H H
0000BC FFFF6C
H H
0000BD FFFF68
H H
0000BD FFFF64
H H
2
OS.
2
OS, which can be started up for either reception or transmission
Upper Bank
FFFF71 FFFF72
H H
FFFF6D FFFF6E
H H
FFFF69 FFFF6A
H H
FFFF65 FFFF66
H H
2
EI OS
*1
*2
*1
*2