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Fujitsu 8FX manual available for free PDF download: Hardware Manual
Fujitsu 8FX Hardware Manual (650 pages)
8-BIT MICROCONTROLLER New 8FX family
Brand:
Fujitsu
| Category:
Computer Hardware
| Size: 8.96 MB
Table of Contents
9
Table of Contents
23
Chapter 1 Memory Access Mode
24
Memory Access Mode
25
Chapter 2 Cpu
26
Dedicated Registers
28
Register Bank Pointer (RP)
29
Direct Bank Pointer (DP)
31
Condition Code Register (CCR)
33
General-Purpose Register
35
Placement of 16-Bit Data in Memory
37
Chapter 3 Clock Controller
38
Overview
46
Oscillation Stabilization Wait Time
49
Registers
50
System Clock Control Register (SYCC)
51
PLL Control Register (PLLC)
52
Oscillation Stabilization Wait Time Setting Register (WATR)
54
Standby Control Register (STBC)
56
System Clock Control Register 2 (SYCC2)
58
Standby Control Register 2 (STBC2)
59
Clock Modes
63
Operations in Low Power Consumption Mode (Standby Mode)
64
Notes On Using Standby Mode
70
Sleep Mode
71
Stop Mode
73
Time-Base Timer Mode
75
Watch Mode
76
Clock Oscillator Circuit
77
Overview of Prescaler
78
Configuration of Prescaler
79
Operation of Prescaler
81
Notes On Using Prescaler
83
Chapter 4 Reset
84
Reset Operation
88
Register
89
Reset Source Register (RSRR)
92
Notes On Using Reset
93
Chapter 5 Interrupts
94
Interrupts
95
Interrupt Level Setting Registers (ILR0 to ILR5)
97
Interrupt Processing
99
Nested Interrupts
100
Interrupt Processing Time
101
Stack Operation During Interrupt Processing
102
Interrupt Processing Stack Area
103
Chapter 6 I/O Port
104
Overview
105
Configuration and Operations
109
Chapter 7 Time-Base Timer
110
Overview
111
Configuration
113
Interrupt
114
Operations and Setting Procedure Example
117
Register
118
Time-Base Timer Control Register (TBTC)
120
Notes On Using Time-Base Timer
121
Chapter 8 Hardware/Software Watchdog Timer
122
Overview
123
Configuration
125
Operations and Setting Procedure Example
128
Register
129
Watchdog Timer Control Register (WDTC)
131
Notes On Using Watchdog Timer
133
Chapter 9 Watch Prescaler
134
Overview
135
Configuration
137
Interrupt
138
Operations and Setting Procedure Example
141
Register
142
Watch Prescaler Control Register (WPCR)
144
Notes On Using Watch Prescaler
145
Chapter 10 Wild Register Function
146
Overview
147
Configuration
149
Operations
150
Registers
151
Wild Register Data Setting Registers (WRDR0 to WRDR2)
152
Wild Register Address Setting Registers (WRAR0 to WRAR2)
153
Wild Register Address Compare Enable Register (WREN)
154
Wild Register Data Test Setting Register (WROR)
155
Typical Hardware Connection Example
157
Chapter 11 8/16-Bit Composite Timer
158
Overview
160
Configuration
163
Channel
164
Pins
165
Interrupts
166
Operation of Interval Timer Function (One-Shot Mode)
168
Operation of Interval Timer Function (Continuous Mode)
170
Operation of Interval Timer Function (Free-Run Mode)
172
Operation of PWM Timer Function (Fixed-Cycle Mode)
174
Operation of PWM Timer Function (Variable-Cycle Mode)
176
11.11 Operation of PWC Timer Function
178
11.12 Operation of Input Capture Function
180
11.13 Operation of Noise Filter
181
11.14 Registers
182
8/16-Bit Composite Timer Status Control Register 0 (Tn0Cr0/Tn1Cr0)
185
8/16-Bit Composite Timer Status Control Register 1 (Tn0Cr1/Tn1Cr1)
189
8/16-Bit Composite Timer Timer Mode Control Register (Tmcrn)
192
8/16-Bit Composite Timer Data Register (Tn0Dr/Tn1Dr)
195
11.15 Notes On Using 8/16-Bit Composite Timer
197
Chapter 12 External Interrupt Circuit
198
Overview
199
Configuration
200
Channels
201
Pin
202
Interrupt
203
Operations and Setting Procedure Example
205
Register
206
External Interrupt Control Register (EIC)
208
Notes On Using External Interrupt Circuit
209
Chapter 13 Interrupt Pin Selection Circuit
210
Overview
211
Configuration
212
Pins
213
Operation
214
Register
215
Interrupt Pin Selection Circuit Control Register (WICR)
218
Notes On Using Interrupt Pin Selection Circuit
219
Chapter 14 Lin-Uart
220
Overview
222
Configuration
223
Reload Counter
227
Pins
228
Interrupts
231
Timing of Receive Interrupt Generation and Flag Set
233
Timing of Transmit Interrupt Generation and Flag Set
235
LIN-UART Baud Rate
237
Baud Rate Setting
241
Reload Counter
243
Operations of LIN-UART and LIN-UART Setting Procedure Example
245
Operations in Asynchronous Mode (Operating Mode 0, 1)
249
Operations in Synchronous Mode (Operating Mode 2)
253
Operations of LIN Function (Operating Mode 3)
256
Serial Pin Direct Access
257
Bidirectional Communication Function (Normal Mode)
259
Master/Slave Mode Communication Function (Multiprocessor Mode)
262
LIN Communication Function
263
Examples of LIN-UART LIN Communication Flow Chart (Operating Mode 3)
265
Registers
266
LIN-UART Serial Control Register (SCR)
268
LIN-UART Serial Mode Register (SMR)
270
LIN-UART Serial Status Register (SSR)
272
LIN-UART Receive Data Register/Lin-Uart Transmit Data Register (RDR/TDR)
274
LIN-UART Extended Status Control Register (ESCR)
277
LIN-UART Extended Communication Control Register (ECCR)
279
LIN-UART Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
280
Notes On Using LIN-UART
286
Chapter 15 8/10-Bit A/D Converter
286
Overview
287
Configuration
289
Pin
290
Interrupt
291
Operations and Setting Procedure Example
294
Registers
295
8/10-Bit A/D Converter Control Register 1 (ADC1)
297
8/10-Bit A/D Converter Control Register 2 (ADC2)
299
8/10-Bit A/D Converter Data Register (Upper/Lower) (ADDH/ADDL)
300
Notes On Using 8/10-Bit A/D Converter
303
Chapter 16 Low-Voltage Detection Reset Circuit
304
Overview
305
Configuration
306
Pins
307
Operation
308
Register
309
LVD Reset Voltage Selection ID Register (LVDR)
311
Chapter 17 Clock Supervisor Counter
312
Overview
313
Configuration
315
Operations
320
Registers
321
Clock Monitoring Data Register (CMDR)
322
Clock Monitoring Control Register (CMCR)
324
Notes On Using Clock Supervisor Counter
327
Chapter 18 8/16-Bit Ppg
328
Overview
329
Configuration
331
Channel
332
Pins
333
Interrupt
334
Operations and Setting Procedure Example
335
8-Bit PPG Independent Mode
337
8-Bit Prescaler + 8-Bit PPG Mode
339
16-Bit PPG Mode
342
Registers
343
8/16-Bit PPG Timer N1 Control Register (Pcn1)
345
8/16-Bit PPG Timer N0 Control Register (Pcn0)
347
8/16-Bit PPG Timer N1/N0 Cycle Setup Buffer Register (Ppsn1/Ppsn0)
348
8/16-Bit PPG Timer N1/N0 Duty Setup Buffer Register (Pdsn1/Pdsn0)
349
8/16-Bit PPG Start Register (PPGS)
351
8/16-Bit PPG Output Reverse Register (REVC)
353
Notes On Using 8/16-Bit PPG
355
Chapter 19 16-Bit Ppg Timer
356
Overview
357
Configuration
359
Channel
360
Pins
361
Interrupts
362
Operations and Setting Procedure Example
366
Registers
367
16-Bit PPG Downcounter Register (Upper/Lower) Ch. N (Pdcrhn/Pdcrln)
368
16-Bit PPG Cycle Setting Buffer Register (Upper/ Lower) Ch. N (Pcsrhn/Pcsrln)
369
16-Bit PPG Duty Setting Buffer Register (Upper/Lower) Ch. N (Pduthn/Pdutln)
370
16-Bit PPG Status Control Register (Upper) Ch. N (Pcnthn)
372
16-Bit PPG Status Control Register (Lower) Ch. N (Pcntln)
374
Notes On Using 16-Bit PPG Timer
375
Chapter 20 16-Bit Reload Timer
376
Overview
378
Configuration
380
Channel
381
Pins
382
Interrupt
383
Operations and Setting Procedure Example
385
Internal Clock Mode
389
Event Count Mode
391
Registers
392
16-Bit Reload Timer Control Status Register (Upper) Ch. N (Tmcsrhn)
394
16-Bit Reload Timer Control Status Register (Lower) Ch. N (Tmcsrln)
396
16-Bit Reload Timer Timer Register (Upper/Lower) Ch. N (Tmrhn/Tmrln)
397
16-Bit Reload Timer Reload Register (Upper/Lower) Ch. N (Tmrlrhn/Tmrlrln)
398
Notes On Using 16-Bit Reload Timer
399
Chapter 21 Multi-Pulse Generator
400
Overview
403
Block Diagram
411
Pins
412
Interrupts
414
Operations
416
Operation of Position Detection
418
Operation of Data Write Control Unit
422
Operation of 16-Bit MPG Output Data Buffer Register (Upper/Lower) (Opdbrhx/Opdbrlx)
424
Operation of Data Transfer of 16-Bit MPG Output Data Register (Upper/Lower)
426
At OPDBRH0 and OPDBRL0 Write
427
At 16-Bit Reload Timer Underflow
429
At Position Detection
431
At Position Detection and Timer Underflow
434
At Position Detection or Timer Underflow
436
At One-Shot Position Detection
437
When One-Shot Position Detection and Reload Timer Underflow
438
When One-Shot Position Detection or Reload Timer Underflow
439
Operation of DTTI Input Control
442
Operation of Noise Cancellation Function
443
Operation of 16-Bit Timer
448
Registers
449
16-Bit MPG Output Control Register (Upper) (OPCUR)
451
16-Bit MPG Output Control Register (Lower) (OPCLR)
453
16-Bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR)
454
16-Bit MPG Output Data Register (Upper) (OPDUR)
456
16-Bit MPG Output Data Register (Lower) (OPDLR)
457
16-Bit MPG Output Data Buffer Register (Upper/Lower) (Opdbrhx/Opdbrlx)
458
16-Bit MPG Output Data Buffer Register (Upper) (Opdbrhx)
460
16-Bit MPG Output Data Buffer Register (Lower) (Opdbrlx)
462
16-Bit MPG Input Control Register (Upper/Lower) (IPCUR/IPCLR)
463
16-Bit MPG Input Control Register (Upper) (IPCUR)
465
16-Bit MPG Input Control Register (Lower) (IPCLR)
467
16-Bit MPG Compare Clear Register (Upper/Lower) (CPCUR/CPCLR)
468
16-Bit MPG Timer Buffer Register (Upper/Lower) (TMBUR/TMBLR)
469
16-Bit MPG Timer Control Status Register (TCSR)
471
16-Bit MPG Noise Cancellation Control Register (NCCR)
472
Notes On Using Multi-Pulse Generator
474
Sample Program for Multi-Pulse Generator
477
Chapter 22 Uart/Sio
478
Overview
479
Configuration
481
Channel
482
Pins
483
Interrupts
484
Operations and Setting Procedure Example
485
Operations in Operation Mode 0
492
Operations in Operation Mode 1
498
Registers
499
UART/SIO Serial Mode Control Register 1 Ch. N (Smc1N)
501
UART/SIO Serial Mode Control Register 2 Ch. N (Smc2N)
503
UART/SIO Serial Status and Data Register Ch. N (Ssrn)
505
UART/SIO Serial Input Data Register Ch. N (Rdrn)
506
UART/SIO Serial Output Data Register Ch. N (Tdrn)
507
Chapter 23 Uart/Sio Dedicated Baud Rate Generator
508
Overview
509
Channel
510
Operations
511
Registers
512
UART/SIO Dedicated Baud Rate Generator Prescaler Select Register Ch. N (Pssrn)
513
UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register Ch. N (Brsrn)
515
Chapter 24 I 2 C Bus Interface
516
Overview
517
Configuration
520
Channel
521
Pins
522
Interrupts
524
Operations and Setting Procedure Example
525
C Bus Interface
533
Function to Wake Up the MCU From Standby Mode
535
Registers
536
I 2 C Bus Control Register 0 Ch. N (Ibcr0N)
539
C Bus Control Register 1 Ch. N (Ibcr1N)
543
I 2 C Bus Status Register Ch. N (Ibsrn)
546
I 2 C Data Register Ch. N (Iddrn)
547
I 2 C Address Register Ch. N (Iaarn)
548
I 2 C Clock Control Register Ch. N (Iccrn)
550
Notes On Using I 2 C Bus Interface
553
Chapter 25 Example of Serial Programming Connection
554
Basic Configuration of Serial Programming Connection
555
Example of Serial Programming Connection
557
Chapter 26 Dual Operation Flash Memory
558
Overview
560
Sector/Bank Configuration
561
Invoking Flash Memory Automatic Algorithm
563
Checking Automatic Algorithm Execution Status
565
Data Polling Flag (DQ7)
567
Toggle Bit Flag (DQ6)
568
Execution Timeout Flag (DQ5)
569
Sector Erase Timer Flag (DQ3)
570
Toggle Bit2 Flag (DQ2)
571
Programming/Erasing Flash Memory
572
Placing Flash Memory in Read/Reset State
573
Programming Data to Flash Memory
575
Erasing All Data From Flash Memory (Chip Erase)
576
Erasing Specific Data From Flash Memory (Sector Erase)
578
Suspending Sector Erase From Flash Memory
579
Resuming Sector Erase of Flash Memory
580
Unlock Bypass Program
581
Operations
583
Flash Security
584
Registers
585
Flash Memory Status Register 2 (FSR2)
588
Flash Memory Status Register (FSR)
591
Flash Memory Sector Write Control Register 0 (SWRE0)
593
Flash Memory Status Register 3 (FSR3)
594
Flash Memory Status Register 4 (FSR4)
602
Notes On Using Dual Operation Flash Memory
603
Chapter 27 Non-Volatile Register (Nvr) Interface
604
Overview
605
Configuration
606
Registers
607
Main CR Clock Trimming Register (Upper) (CRTH)
608
Main CR Clock Trimming Register (Lower) (CRTL)
609
Main CR Clock Temperature Dependent Adjustment Register (CRTDA)
610
Watchdog Timer Selection ID Register (Upper/Lower) (WDTH/WDTL)
611
Notes On Main CR Clock Trimming
613
Notes On Using NVR Interface
615
Chapter 28 Comparator
616
Overview
617
Configuration
619
Pins
620
Interrupt
621
Operations and Setting Procedure Example
622
Register
623
Comparator Control Register (CMR0C)
625
Chapter 29 System Configuration Controller
626
Overview
627
Register
628
System Configuration Register (SYSC)
630
Notes On Using Controller
631
Appendix
632
APPENDIX A Instruction Overview
635
Addressing
635
A.1 Addressing
639
Special Instruction
639
A.2 Special Instruction
647
APPENDIX A Instruction Overview
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