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Fujitsu 8FX Hardware Manual (650 pages)

8-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Control Units | Size: 8.96 MB

Table Of Contents9................................................................................................................................................................

Chapter 1 Memory Access Mode23................................................................................................................................................................

Memory Access Mode24................................................................................................................................................................

Chapter 2 Cpu25................................................................................................................................................................

Dedicated Registers26................................................................................................................................................................

Register Bank Pointer (rp)28................................................................................................................................................................

Direct Bank Pointer (dp)29................................................................................................................................................................

Condition Code Register (ccr)31................................................................................................................................................................

General-purpose Register33................................................................................................................................................................

Placement Of 16-bit Data In Memory35................................................................................................................................................................

Chapter 3 Clock Controller37................................................................................................................................................................

Overview38................................................................................................................................................................

Clock Modes42................................................................................................................................................................

Oscillation Stabilization Wait Time46................................................................................................................................................................

Registers49................................................................................................................................................................

System Clock Control Register (sycc)50................................................................................................................................................................

Pll Control Register (pllc)51................................................................................................................................................................

Oscillation Stabilization Wait Time Setting Register (watr)52................................................................................................................................................................

Standby Control Register (stbc)54................................................................................................................................................................

System Clock Control Register 2 (sycc2)56................................................................................................................................................................

Standby Control Register 2 (stbc2)58................................................................................................................................................................

Operations In Low Power Consumption Mode (standby Mode)63................................................................................................................................................................

Notes On Using Standby Mode64................................................................................................................................................................

Sleep Mode70................................................................................................................................................................

Stop Mode71................................................................................................................................................................

Time-base Timer Mode73................................................................................................................................................................

Watch Mode75................................................................................................................................................................

Clock Oscillator Circuit76................................................................................................................................................................

Overview Of Prescaler77................................................................................................................................................................

Configuration Of Prescaler78................................................................................................................................................................

Operation Of Prescaler79................................................................................................................................................................

Notes On Using Prescaler81................................................................................................................................................................

Chapter 4 Reset83................................................................................................................................................................

Reset Operation84................................................................................................................................................................

Register88................................................................................................................................................................

Reset Source Register (rsrr)89................................................................................................................................................................

Notes On Using Reset92................................................................................................................................................................

Chapter 5 Interrupts93................................................................................................................................................................

Interrupts94................................................................................................................................................................

Interrupt Level Setting Registers (ilr0 To Ilr5)95................................................................................................................................................................

Interrupt Processing97................................................................................................................................................................

Nested Interrupts99................................................................................................................................................................

Interrupt Processing Time100................................................................................................................................................................

Stack Operation During Interrupt Processing101................................................................................................................................................................

Interrupt Processing Stack Area102................................................................................................................................................................

Chapter 6 I/o Port103................................................................................................................................................................

Configuration And Operations105................................................................................................................................................................

Chapter 7 Time-base Timer109................................................................................................................................................................

Configuration111................................................................................................................................................................

Interrupt113................................................................................................................................................................

Operations And Setting Procedure Example114................................................................................................................................................................

Time-base Timer Control Register (tbtc)118................................................................................................................................................................

Notes On Using Time-base Timer120................................................................................................................................................................

Chapter 8 Hardware/software Watchdog Timer128................................................................................................................................................................

Watchdog Timer Control Register (wdtc)129................................................................................................................................................................

Notes On Using Watchdog Timer131................................................................................................................................................................

Chapter 9 Watch Prescaler133................................................................................................................................................................

Watch Prescaler Control Register (wpcr)142................................................................................................................................................................

Notes On Using Watch Prescaler144................................................................................................................................................................

Chapter 10 Wild Register Function145................................................................................................................................................................

Operations149................................................................................................................................................................

Wild Register Data Setting Registers (wrdr0 To Wrdr2)151................................................................................................................................................................

Wild Register Address Setting Registers (wrar0 To Wrar2)152................................................................................................................................................................

Wild Register Address Compare Enable Register (wren)153................................................................................................................................................................

Wild Register Data Test Setting Register (wror)154................................................................................................................................................................

Typical Hardware Connection Example155................................................................................................................................................................

Chapter 11 8/16-bit Composite Timer157................................................................................................................................................................

Channel163................................................................................................................................................................

Pins164................................................................................................................................................................

Operation Of Interval Timer Function (one-shot Mode)166................................................................................................................................................................

Operation Of Interval Timer Function (continuous Mode)168................................................................................................................................................................

Operation Of Interval Timer Function (free-run Mode)170................................................................................................................................................................

Operation Of Pwm Timer Function (fixed-cycle Mode)172................................................................................................................................................................

Operation Of Pwm Timer Function (variable-cycle Mode)174................................................................................................................................................................

Operation Of Pwc Timer Function176................................................................................................................................................................

Operation Of Input Capture Function178................................................................................................................................................................

Operation Of Noise Filter180................................................................................................................................................................

Bit Composite Timer Status Control Register 0 (tn0cr0/tn1cr0)182................................................................................................................................................................

Bit Composite Timer Status Control Register 1 (tn0cr1/tn1cr1)185................................................................................................................................................................

Bit Composite Timer Timer Mode Control Register (tmcrn)189................................................................................................................................................................

Bit Composite Timer Data Register (tn0dr/tn1dr)192................................................................................................................................................................

Notes On Using 8/16-bit Composite Timer195................................................................................................................................................................

Chapter 12 External Interrupt Circuit197................................................................................................................................................................

Channels200................................................................................................................................................................

External Interrupt Control Register (eic)206................................................................................................................................................................

Notes On Using External Interrupt Circuit208................................................................................................................................................................

Chapter 13 Interrupt Pin Selection Circuit209................................................................................................................................................................

Operation213................................................................................................................................................................

Interrupt Pin Selection Circuit Control Register (wicr)215................................................................................................................................................................

Notes On Using Interrupt Pin Selection Circuit218................................................................................................................................................................

Chapter 14 Lin-uart219................................................................................................................................................................

Reload Counter223................................................................................................................................................................

Timing Of Receive Interrupt Generation And Flag Set231................................................................................................................................................................

Timing Of Transmit Interrupt Generation And Flag Set233................................................................................................................................................................

Lin-uart Baud Rate235................................................................................................................................................................

Baud Rate Setting237................................................................................................................................................................

Operations Of Lin-uart And Lin-uart Setting Procedure Example243................................................................................................................................................................

Operations In Asynchronous Mode (operating Mode 0, 1)245................................................................................................................................................................

Operations In Synchronous Mode (operating Mode 2)249................................................................................................................................................................

Operations Of Lin Function (operating Mode 3)253................................................................................................................................................................

Serial Pin Direct Access256................................................................................................................................................................

Bidirectional Communication Function (normal Mode)257................................................................................................................................................................

Master/slave Mode Communication Function (multiprocessor Mode)259................................................................................................................................................................

Lin Communication Function262................................................................................................................................................................

Examples Of Lin-uart Lin Communication Flow Chart (operating Mode 3)263................................................................................................................................................................

Lin-uart Serial Control Register (scr)266................................................................................................................................................................

Lin-uart Serial Mode Register (smr)268................................................................................................................................................................

Lin-uart Serial Status Register (ssr)270................................................................................................................................................................

Lin-uart Receive Data Register/lin-uart Transmit Data Register (rdr/tdr)272................................................................................................................................................................

Lin-uart Extended Status Control Register (escr)274................................................................................................................................................................

Lin-uart Extended Communication Control Register (eccr)277................................................................................................................................................................

Lin-uart Baud Rate Generator Registers 1, 0 (bgr1, Bgr0)279................................................................................................................................................................

Notes On Using Lin-uart280................................................................................................................................................................

Chapter 15 8/10-bit A/d Converter285................................................................................................................................................................

Bit A/d Converter Control Register 1 (adc1)295................................................................................................................................................................

Bit A/d Converter Control Register 2 (adc2)297................................................................................................................................................................

Bit A/d Converter Data Register (upper/lower) (addh/addl)299................................................................................................................................................................

Notes On Using 8/10-bit A/d Converter300................................................................................................................................................................

Chapter 16 Low-voltage Detection Reset Circuit303................................................................................................................................................................

Lvd Reset Voltage Selection Id Register (lvdr)309................................................................................................................................................................

Chapter 17 Clock Supervisor Counter311................................................................................................................................................................

Clock Monitoring Data Register (cmdr)321................................................................................................................................................................

Clock Monitoring Control Register (cmcr)322................................................................................................................................................................

Notes On Using Clock Supervisor Counter324................................................................................................................................................................

Chapter 18 8/16-bit Ppg327................................................................................................................................................................

Bit Ppg Independent Mode335................................................................................................................................................................

Bit Prescaler + 8-bit Ppg Mode337................................................................................................................................................................

Bit Ppg Mode339................................................................................................................................................................

Bit Ppg Timer N1 Control Register (pcn1)343................................................................................................................................................................

Bit Ppg Timer N0 Control Register (pcn0)345................................................................................................................................................................

Bit Ppg Timer N1/n0 Cycle Setup Buffer Register (ppsn1/ppsn0)347................................................................................................................................................................

Bit Ppg Timer N1/n0 Duty Setup Buffer Register (pdsn1/pdsn0)348................................................................................................................................................................

Bit Ppg Start Register (ppgs)349................................................................................................................................................................

Bit Ppg Output Reverse Register (revc)351................................................................................................................................................................

Notes On Using 8/16-bit Ppg353................................................................................................................................................................

Chapter 19 16-bit Ppg Timer355................................................................................................................................................................

Bit Ppg Downcounter Register (upper/lower) Ch. N (pdcrhn/pdcrln)367................................................................................................................................................................

Bit Ppg Cycle Setting Buffer Register (upper/ Lower) Ch. N Pcsrhn/pcsrln)368................................................................................................................................................................

Bit Ppg Duty Setting Buffer Register (upper/lower) Ch. N (pduthn/pdutln)369................................................................................................................................................................

Bit Ppg Status Control Register (upper) Ch. N (pcnthn)370................................................................................................................................................................

Bit Ppg Status Control Register (lower) Ch. N (pcntln)372................................................................................................................................................................

Notes On Using 16-bit Ppg Timer374................................................................................................................................................................

Chapter 20 16-bit Reload Timer375................................................................................................................................................................

Internal Clock Mode385................................................................................................................................................................

Event Count Mode389................................................................................................................................................................

Bit Reload Timer Control Status Register (upper) Ch. N (tmcsrhn)392................................................................................................................................................................

Bit Reload Timer Control Status Register (lower) Ch. N (tmcsrln)394................................................................................................................................................................

Bit Reload Timer Timer Register (upper/lower) Ch. N (tmrhn/tmrln)396................................................................................................................................................................

Bit Reload Timer Reload Register (upper/lower) Ch. N (tmrlrhn/tmrlrln)397................................................................................................................................................................

Notes On Using 16-bit Reload Timer398................................................................................................................................................................

Chapter 21 Multi-pulse Generator399................................................................................................................................................................

Block Diagram403................................................................................................................................................................

Operation Of Position Detection416................................................................................................................................................................

Operation Of Data Write Control Unit418................................................................................................................................................................

Operation Of 16-bit Mpg Output Data Buffer Register (upper/lower Opdbrhx/opdbrlx)422................................................................................................................................................................

Operation Of Data Transfer Of 16-bit Mpg Output Data Register (upper/lower)424................................................................................................................................................................

At Opdbrh0 And Opdbrl0 Write426................................................................................................................................................................

At 16-bit Reload Timer Underflow427................................................................................................................................................................

At Position Detection429................................................................................................................................................................

At Position Detection And Timer Underflow431................................................................................................................................................................

At Position Detection Or Timer Underflow434................................................................................................................................................................

At One-shot Position Detection436................................................................................................................................................................

When One-shot Position Detection And Reload Timer Underflow437................................................................................................................................................................

When One-shot Position Detection Or Reload Timer Underflow438................................................................................................................................................................

Operation Of Dtti Input Control439................................................................................................................................................................

Operation Of Noise Cancellation Function442................................................................................................................................................................

Operation Of 16-bit Timer443................................................................................................................................................................

Bit Mpg Output Control Register (upper) (opcur)449................................................................................................................................................................

Bit Mpg Output Control Register (upper)449................................................................................................................................................................

Bit Mpg Output Control Register (lower) (opclr)451................................................................................................................................................................

Bit Mpg Output Control Register (lower)451................................................................................................................................................................

Bit Mpg Output Data Register (upper/lower) (opdur/opdlr)453................................................................................................................................................................

Bit Mpg Output Data Register (upper) (opdur)454................................................................................................................................................................

Bit Mpg Output Data Register (upper)454................................................................................................................................................................

Bit Mpg Output Data Register (lower) (opdlr)456................................................................................................................................................................

Bit Mpg Output Data Register (lower)456................................................................................................................................................................

Bit Mpg Output Data Buffer Register (upper/lower) (opdbrhx/opdbrlx)457................................................................................................................................................................

Bit Mpg Output Data Buffer Register (upper) (opdbrhx)458................................................................................................................................................................

Bit Mpg Output Data Buffer Register (upper)458................................................................................................................................................................

Bit Mpg Output Data Buffer Register (lower) (opdbrlx)460................................................................................................................................................................

Bit Mpg Output Data Buffer Register (lower)460................................................................................................................................................................

Bit Mpg Input Control Register (upper/lower) (ipcur/ipclr)462................................................................................................................................................................

Bit Mpg Input Control Register (upper) (ipcur)463................................................................................................................................................................

Bit Mpg Input Control Register (upper)463................................................................................................................................................................

Bit Mpg Input Control Register (lower) (ipclr)465................................................................................................................................................................

Bit Mpg Input Control Register (lower)465................................................................................................................................................................

Bit Mpg Compare Clear Register (upper/lower) (cpcur/cpclr)467................................................................................................................................................................

Bit Mpg Timer Buffer Register (upper/lower) (tmbur/tmblr)468................................................................................................................................................................

Bit Mpg Timer Control Status Register (tcsr)469................................................................................................................................................................

Bit Mpg Noise Cancellation Control Register (nccr)471................................................................................................................................................................

Bit Mpg Noise Cancellation Control Register471................................................................................................................................................................

Notes On Using Multi-pulse Generator472................................................................................................................................................................

Sample Program For Multi-pulse Generator474................................................................................................................................................................

Chapter 22 Uart/sio477................................................................................................................................................................

Operations In Operation Mode 0485................................................................................................................................................................

Operations In Operation Mode 1492................................................................................................................................................................

Uart/sio Serial Mode Control Register 1 Ch. N (smc1n)499................................................................................................................................................................

Uart/sio Serial Mode Control Register 2 Ch. N (smc2n)501................................................................................................................................................................

Uart/sio Serial Status And Data Register Ch. N (ssrn)503................................................................................................................................................................

Uart/sio Serial Input Data Register Ch. N (rdrn)505................................................................................................................................................................

Uart/sio Serial Output Data Register Ch. N (tdrn)506................................................................................................................................................................

Chapter 23 Uart/sio Dedicated Baud Rate Generator507................................................................................................................................................................

Chapter 24 I 2 C Bus Interface519................................................................................................................................................................

Function To Wake Up The Mcu From Standby Mode533................................................................................................................................................................

Chapter 25 Example Of Serial Programming Connection553................................................................................................................................................................

Basic Configuration Of Serial Programming Connection554................................................................................................................................................................

Example Of Serial Programming Connection555................................................................................................................................................................

Chapter 26 Dual Operation Flash Memory557................................................................................................................................................................

Sector/bank Configuration560................................................................................................................................................................

Invoking Flash Memory Automatic Algorithm561................................................................................................................................................................

Checking Automatic Algorithm Execution Status563................................................................................................................................................................

Data Polling Flag (dq7)565................................................................................................................................................................

Toggle Bit Flag (dq6)567................................................................................................................................................................

Execution Timeout Flag (dq5)568................................................................................................................................................................

Sector Erase Timer Flag (dq3)569................................................................................................................................................................

Toggle Bit2 Flag (dq2)570................................................................................................................................................................

Programming/erasing Flash Memory571................................................................................................................................................................

Placing Flash Memory In Read/reset State572................................................................................................................................................................

Programming Data To Flash Memory573................................................................................................................................................................

Erasing All Data From Flash Memory (chip Erase)575................................................................................................................................................................

Erasing Specific Data From Flash Memory (sector Erase)576................................................................................................................................................................

Suspending Sector Erase From Flash Memory578................................................................................................................................................................

Resuming Sector Erase Of Flash Memory579................................................................................................................................................................

Unlock Bypass Program580................................................................................................................................................................

Flash Security583................................................................................................................................................................

Flash Memory Status Register 2 (fsr2)585................................................................................................................................................................

Flash Memory Status Register (fsr)588................................................................................................................................................................

Flash Memory Sector Write Control Register 0 (swre0)591................................................................................................................................................................

Flash Memory Status Register 3 (fsr3)593................................................................................................................................................................

Flash Memory Status Register 4 (fsr4)594................................................................................................................................................................

Notes On Using Dual Operation Flash Memory602................................................................................................................................................................

Chapter 27 Non-volatile Register (nvr) Interface603................................................................................................................................................................

Main Cr Clock Trimming Register (upper) (crth)607................................................................................................................................................................

Main Cr Clock Trimming Register (lower) (crtl)608................................................................................................................................................................

Main Cr Clock Temperature Dependent Adjustment Register (crtda)609................................................................................................................................................................

Watchdog Timer Selection Id Register (upper/lower) (wdth/wdtl)610................................................................................................................................................................

Notes On Main Cr Clock Trimming611................................................................................................................................................................

Notes On Using Nvr Interface613................................................................................................................................................................

Chapter 28 Comparator615................................................................................................................................................................

Comparator Control Register (cmr0c)623................................................................................................................................................................

Chapter 29 System Configuration Controller625................................................................................................................................................................

System Configuration Register (sysc)628................................................................................................................................................................

Notes On Using Controller630................................................................................................................................................................

Appendix631................................................................................................................................................................

Appendix A Instruction Overview632................................................................................................................................................................

A.1 Addressing635................................................................................................................................................................

A.2 Special Instruction639................................................................................................................................................................